linux-kernel - Re: [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <1469611556.11841.77.camel@mtksdaap41>
Date:	Wed, 27 Jul 2016 17:25:56 +0800
From:	CK Hu <ck.hu@...iatek.com>
To:	Bibby Hsieh <bibby.hsieh@...iatek.com>
CC:	Mark Rutland <mark.rutland@....com>, <devicetree@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>,
	<linux-mediatek@...ts.infradead.org>,
	Rob Herring <robh+dt@...nel.org>,
	"Pawel Moll" <pawel.moll@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will.deacon@....com>,
	"Matthias Brugger" <matthias.bgg@...il.com>,
	Daniel Kurtz <djkurtz@...omium.org>,
	Yingjoe Chen <yingjoe.chen@...iatek.com>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	James Liao <jamesjj.liao@...iatek.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@....com>,
	YH Huang <yh.huang@...iatek.com>,
	Yong Wu <yong.wu@...iatek.com>,
	Eddie Huang <eddie.huang@...iatek.com>,
	"dawei.chien@...iatek.com" <dawei.chien@...iatek.com>,
	Chunfeng Yun <chunfeng.yun@...iatek.com>,
	Junzhi Zhao <junzhi.zhao@...iatek.com>,
	Philipp Zabel <p.zabel@...gutronix.de>
Subject: Re: [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support

Hi, Bibby:

On Wed, 2016-07-27 at 16:25 +0800, Bibby Hsieh wrote:
> If MT8173 can support HDMI 4K resoultion, the
> VENCPLL should be configured to 800MHZ.
> We didn't set VENCPLL directly, we set the
> mm_sel to 400MHz statically in the board device tree.

You may rewrite the description as below:

'To support HDMI 4K resolution, mmsys need clock mm_sel to be 400MHz.'

You need not to mention VENCPLL because it's controlled by clock driver.

> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@...iatek.com>
> ---
> Changes since v2:
>  - Align the clocks of dpi0 node.
> 
> Changes since v1:
>  - Do not set the VENCPLL by clk_set_rate
>    at display driver.
>  - Configure the mm_sel to 400MHz statically
>    in the board device tree.
> ---
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 78529e4..9c22204 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -690,7 +690,9 @@
>  			compatible = "mediatek,mt8173-mmsys", "syscon";
>  			reg = <0 0x14000000 0 0x1000>;
>  			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +			clocks = <&topckgen CLK_TOP_MM_SEL>;
>  			#clock-cells = <1>;
> +			clock-frequency  = <400000000>;
>  		};
>  
>  		ovl0: ovl@...0c000 {

Regards,
CK