linux-kernel - Re: [PATCH v4 1/2] of: add J-Core interrupt controller bindings

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Message-ID: <20160727130007.GZ15995@brightrain.aerifal.cx>
Date:	Wed, 27 Jul 2016 09:00:07 -0400
From:	Rich Felker <dalias@...c.org>
To:	Mark Rutland <mark.rutland@....com>
Cc:	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-sh@...r.kernel.org, Jason Cooper <jason@...edaemon.net>,
	Marc Zyngier <marc.zyngier@....com>,
	Rob Herring <robh+dt@...nel.org>,
	Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH v4 1/2] of: add J-Core interrupt controller bindings

On Wed, Jul 27, 2016 at 11:05:05AM +0100, Mark Rutland wrote:
> On Wed, Jul 27, 2016 at 05:35:09AM +0000, Rich Felker wrote:
> > Signed-off-by: Rich Felker <dalias@...c.org>
> > ---
> >  .../bindings/interrupt-controller/jcore,aic.txt    | 26 ++++++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > new file mode 100644
> > index 0000000..b7a56ad
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > @@ -0,0 +1,26 @@
> > +J-Core Advanced Interrupt Controller
> > +
> > +Required properties:
> > +
> > +- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
> > +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> > +  the "aic2" core with 64 interrupts.
> > +
> > +- reg: Memory region(s) for configuration. For SMP, there should be one
> > +  region per cpu, indexed by the sequential, zero-based hardware cpu
> > +  number (which is also the logical cpu number).
> 
> Nit: remove the bit about the logical number. That's a linux detail that
> doesn't belong in the binding.

OK.

> > +- interrupt-controller: Identifies the node as an interrupt controller
> > +
> > +- #interrupt-cells: Specifies the number of cells needed to encode an
> > +  interrupt source. The value shall be 1.
> 
> .... where the value encoded in that cell is?
> 
> I guess it's the zero-based index of the interrupt?
> 
> No flags? Can the AIC only do one trigger type?

This was asked before. The AIC does all the interrupt control (aside
from the cpu's main imask status) and does not expose trigger types or
require any kind of ack/eoi from the software. If you'd like to know
more about the motivations behind how it works I could ask on the
j-core list but for the purpose of the bindings and driver I'm just
documenting/supporting what the existing hw design does.

Rich