linux-kernel - [RESEND PATCH v2 0/8] fix and optimize some clock configuration for the RK3399 platfom

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <1470045224-31854-1-git-send-email-zhengxing@rock-chips.com>
Date:	Mon,  1 Aug 2016 17:53:35 +0800
From:	Xing Zheng <zhengxing@...k-chips.com>
To:	heiko@...ech.de
Cc:	linux-rockchip@...ts.infradead.org, dianders@...omium.org,
	briannorris@...omium.org, huangtao@...k-chips.com,
	zhangqing@...k-chips.com, Xing Zheng <zhengxing@...k-chips.com>,
	devicetree@...r.kernel.org, Jianqun Xu <jay.xu@...k-chips.com>,
	frank.wang@...k-chips.com, shawn.lin@...k-chips.com,
	Michael Turquette <mturquette@...libre.com>,
	Kumar Gala <galak@...eaurora.org>,
	linux-kernel@...r.kernel.org,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>, wulf@...k-chips.com,
	Mark Rutland <mark.rutland@....com>, linux-clk@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org
Subject: [RESEND PATCH v2 0/8] fix and optimize some clock configuration for the RK3399 platfom


Hi:
  In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.

Changes in v2:
- add the patch "fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src"
- add the patch "fix incorrect GATE bits for {c, g}pll_aclk_perihp_src"

Elaine Zhang (1):
  clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie

Xing Zheng (7):
  clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
  clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
  clk: rockchip: rk3399: fix incorrect parent for rk3399's {c,
    g}pll_aclk_perihp_src
  clk: rockchip: rk3399: fix incorrect GATE bits for {c,
    g}pll_aclk_perihp_src
  clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
  clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
  clk: rockchip: rk3399: Add support frac mode frequencies

 drivers/clk/rockchip/clk-rk3399.c      |   41 ++++++++++++++++++++++++--------
 include/dt-bindings/clock/rk3399-cru.h |    2 ++
 2 files changed, 33 insertions(+), 10 deletions(-)

-- 
1.7.9.5