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Message-Id: <1470025389-4094-2-git-send-email-zhengxing@rock-chips.com>
Date: Mon, 1 Aug 2016 12:23:04 +0800
From: Xing Zheng <zhengxing@...k-chips.com>
To: heiko@...ech.de
Cc: linux-rockchip@...ts.infradead.org, dianders@...omium.org,
briannorris@...omium.org, huangtao@...k-chips.com,
zhangqing@...k-chips.com, Xing Zheng <zhengxing@...k-chips.com>,
frank.wang@...k-chips.com, wulf@...k-chips.com,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Jianqun Xu <jay.xu@...k-chips.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [RESEND PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng <zhengxing@...k-chips.com>
---
include/dt-bindings/clock/rk3399-cru.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..c4d8311 100644
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -131,6 +131,8 @@
#define SCLK_DPHY_RX0_CFG 165
#define SCLK_RMII_SRC 166
#define SCLK_PCIEPHY_REF100M 167
+#define SCLK_USBPHY0_480M_SRC 168
+#define SCLK_USBPHY1_480M_SRC 169
#define DCLK_VOP0 180
#define DCLK_VOP1 181
--
1.7.9.5
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