linux-kernel - Re: [PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq

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Message-ID: <CAD=FV=X1ZAhzBrFukvE9BxdFmgo8dj4GKjZ9EmPLTagHfO-ufg@mail.gmail.com>
Date:	Tue, 2 Aug 2016 17:49:24 -0700
From:	Doug Anderson <dianders@...omium.org>
To:	Xing Zheng <zhengxing@...k-chips.com>
Cc:	Heiko Stübner <heiko@...ech.de>,
	"open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
	Brian Norris <briannorris@...omium.org>,
	Tao Huang <huangtao@...k-chips.com>,
	zhangqing <zhangqing@...k-chips.com>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>,
	linux-clk <linux-clk@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] clk: rockchip: rk3399: add pll up and down when change
 pll freq

Xing,

On Tue, Aug 2, 2016 at 6:13 AM, Xing Zheng <zhengxing@...k-chips.com> wrote:
> From: Elaine Zhang <zhangqing@...k-chips.com>
>
> The suggestion that is from IC designer, the correct pll sequence setting
> should be like these:
> ----
>   set pll to slow mode or other plls
>   set pll down
>   set pll params
>   set pll up
>   wait pll lock status
>   set pll to normal mode
> ----
>
> Hence, there are potential risks that we need to fix:
> rockchip_rk3399_wait_pll_lock - timeout waiting for pll to lock
> rockchip_rk3399_pll_set_params - pll update unsucessful, trying to restore old params

I still don't understand how that groks with the statement in the TRM:

> In most cases the PLL programming can be changed on-the-fly and the PLL will simply slew to the new frequency

That makes it sound like these PLLs are super great at dynamic updates.