linux-kernel - Re: Support for configurable PCIe endpoint

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Date:	Thu, 04 Aug 2016 13:13:06 +0200
From:	Arnd Bergmann <arnd@...db.de>
To:	Kishon Vijay Abraham I <kishon@...com>
Cc:	Joao Pinto <Joao.Pinto@...opsys.com>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	Jingoo Han <jingoohan1@...il.com>,
	Pratyush Anand <pratyush.anand@...il.com>,
	Ley Foon Tan <lftan@...era.com>,
	Rob Herring <robh@...nel.org>,
	Tanmay Inamdar <tinamdar@....com>,
	Roy Zang <tie-fei.zang@...escale.com>,
	Mingkai Hu <mingkai.hu@...escale.com>,
	Minghuan Lian <minghuan.Lian@...escale.com>,
	Richard Zhu <Richard.Zhu@...escale.com>,
	Lucas Stach <l.stach@...gutronix.de>,
	Murali Karicheri <m-karicheri2@...com>,
	Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
	Jason Cooper <jason@...edaemon.net>,
	Thierry Reding <thierry.reding@...il.com>,
	Simon Horman <horms@...ge.net.au>,
	Zhou Wang <wangzhou1@...ilicon.com>,
	Gabriele Paoloni <gabriele.paoloni@...wei.com>,
	Stanimir Varbanov <svarbanov@...sol.com>,
	David Daney <david.daney@...ium.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-omap@...r.kernel.org" <linux-omap@...r.kernel.org>,
	Carlos Palminha <CARLOS.PALMINHA@...opsys.com>
Subject: Re: Support for configurable PCIe endpoint

On Thursday, August 4, 2016 3:32:01 PM CEST Kishon Vijay Abraham I wrote:
> On Wednesday 03 August 2016 07:09 PM, Joao Pinto wrote:
> > 
> > You are rising a topic that we are also addressing in Synopsys.
> > 
> > For the PCIe RC hardware validation we are currently using the standard
> > pcie-designware and pcie-designware-plat drivers.
> > 
> > For the Endpoint we have to use an internal software package. Its main purpose
> > is to initialize the IP registers, eDMA channels and make data transfer to prove
> > that the everything is working properly. This is done in 2 levels, a custom
> > driver built and loaded and an application that makes some ioctl to the driver
> > executing some interesting functions to check the Endpoint status and make some
> > data exchange.
> 
> hmm.. the platform I have doesn't have a DMA in PCIe IP
> (http://www.ti.com/lit/ug/spruhz6g/spruhz6g.pdf). So in your testing does the
> EP access RC memory? i.e the driver in the RC allocates memory from it's DDR
> and gives it's DDR address to the EP. The EP then transfers data to this
> address. (This is a typical use case with ethernet PCIe cards). IIUC that's not
> simple with configurable EPs. I'd like to know more about your testing though.


What's the difference between using the EDMA on that chip or a DMA engine
that is part of the PCIe bridge?

	Arnd