linux-kernel - [PATCH 2/3] perf/x86/intel/uncore: handle non-standard counter offset

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Message-Id: <1471037426-25986-2-git-send-email-kan.liang@intel.com>
Date:	Fri, 12 Aug 2016 17:30:25 -0400
From:	Kan Liang <kan.liang@...el.com>
To:	peterz@...radead.org, tglx@...utronix.de, mingo@...hat.com,
	linux-kernel@...r.kernel.org
Cc:	eranian@...gle.com, andi@...stfloor.org,
	Kan Liang <kan.liang@...el.com>
Subject: [PATCH 2/3] perf/x86/intel/uncore: handle non-standard counter offset

From: Stephane Eranian <eranian@...gle.com>

The offset of the counters for UPI and M2M boxes on Skylake server is
non-standard (8 bytes apart).

This patch introduces a custom flag UNCORE_BOX_FLAG_CTL_OFFS8 to
specially handle it.

Signed-off-by: Stephane Eranian <eranian@...gle.com>
Signed-off-by: Kan Liang <kan.liang@...el.com>
---
 arch/x86/events/intel/uncore.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
index 78b9c23..a43175f 100644
--- a/arch/x86/events/intel/uncore.h
+++ b/arch/x86/events/intel/uncore.h
@@ -120,6 +120,7 @@ struct intel_uncore_box {
 };
 
 #define UNCORE_BOX_FLAG_INITIATED	0
+#define UNCORE_BOX_FLAG_CTL_OFFS8	1 /* event config registers are 8-byte apart */
 
 struct uncore_event_desc {
 	struct kobj_attribute attr;
@@ -172,6 +173,9 @@ static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
 static inline
 unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
 {
+	if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags))
+		return idx * 8 + box->pmu->type->event_ctl;
+
 	return idx * 4 + box->pmu->type->event_ctl;
 }
 
-- 
2.5.5