lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <57B46073.8090800@arm.com>
Date:	Wed, 17 Aug 2016 14:02:43 +0100
From:	Marc Zyngier <marc.zyngier@....com>
To:	Sudeep Holla <sudeep.holla@....com>, linux-kernel@...r.kernel.org
Cc:	Christopher Covington <cov@...eaurora.org>,
	Prashanth Prakash <pprakash@...eaurora.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Jason Cooper <jason@...edaemon.net>
Subject: Re: [PATCH v2] irqchip/gicv3: remove disabling redistributor and
 group1 non-secure interrupts

On 17/08/16 13:49, Sudeep Holla wrote:
> As per the GICv3 specification, to power down a processor using GICv3
> and allow automatic power-on if an interrupt must be sent to a processor,
> software must set Enable to zero for all interrupt groups(by writing
> to GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate.
> 
> When commit 3708d52fc6bb ("irqchip: gic-v3: Implement CPU PM notifier")
> was introduced there were no firmware implementations(in particular PSCI)
> handling this.
> 
> Linux kernel may not be aware of the CPU power state details and might
> fail to identify the power states that require quiescing the CPU
> interface. Even if it can be aware of those details, it can't determine
> which CPU power state have been triggered at the platform level and how
> the power control is implemented.
> 
> This patch make disabling redistributor and group1 non-secure interrupts
> in the power down path and re-enabling of redistributor in the power-up
> path conditional. It will be handled in the kernel if and only if the
> non-secure accesses are permitted to access and modify control registers.
> It is left to the platform implementation otherwise.
> 
> Cc: Marc Zyngier <marc.zyngier@....com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
> Cc: Thomas Gleixner <tglx@...utronix.de>
> Cc: Jason Cooper <jason@...edaemon.net>
> Tested-by: Christopher Covington <cov@...eaurora.org>
> Signed-off-by: Sudeep Holla <sudeep.holla@....com>
> ---
>  drivers/irqchip/irq-gic-v3.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> v1->v2:
> 	- Moved gic_dist_security_disabled inside CONFIG_CPU_PM to fix
> 	  the build warning triggered otherwise.
> 
> Hi Marc,
> 
> Consider this as a fix for v4.8 as it fixes CPUIdle related boot hang on
> Qualcomm QDF2432 platform.

Applied, thanks.

	M.
-- 
Jazz is not dead. It just smells funny...

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ