linux-kernel - [PATCH v11 7/9] reset: mediatek: Add MT2701 reset driver

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Message-ID: <1471584896-9986-8-git-send-email-erin.lo@mediatek.com>
Date:   Fri, 19 Aug 2016 13:34:54 +0800
From:   Erin Lo <erin.lo@...iatek.com>
To:     Matthias Brugger <matthias.bgg@...il.com>,
        Mike Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Rob Herring <robh@...nel.org>
CC:     Arnd Bergmann <arnd@...db.de>,
        Sascha Hauer <kernel@...gutronix.de>,
        Daniel Kurtz <djkurtz@...omium.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-mediatek@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
        <srv_heupstream@...iatek.com>,
        Shunli Wang <shunli.wang@...iatek.com>,
        James Liao <jamesjj.liao@...iatek.com>,
        Erin Lo <erin.lo@...iatek.com>
Subject: [PATCH v11 7/9] reset: mediatek: Add MT2701 reset driver

From: Shunli Wang <shunli.wang@...iatek.com>

In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.

Signed-off-by: Shunli Wang <shunli.wang@...iatek.com>
Signed-off-by: James Liao <jamesjj.liao@...iatek.com>
Signed-off-by: Erin Lo <erin.lo@...iatek.com>
Tested-by: John Crispin <blogic@...nwrt.org>
Acked-by: Philipp Zabel <p.zabel@...gutronix.de>
---
 drivers/clk/mediatek/clk-mt2701-hif.c | 2 ++
 drivers/clk/mediatek/clk-mt2701.c     | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 33ead83..0ca0537 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -55,6 +55,8 @@ static void mtk_hifsys_init(struct device_node *node)
 	if (r)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
+
+	mtk_register_reset_controller(node, 1, 0x34);
 }
 
 static const struct of_device_id of_match_clk_mt2701_hif[] = {
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index f64dc4e..9dab533 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -791,6 +791,8 @@ static void mtk_infrasys_init(struct device_node *node)
 	if (r)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
+
+	mtk_register_reset_controller(node, 2, 0x30);
 }
 
 static const struct mtk_gate_regs peri0_cg_regs = {
@@ -911,6 +913,8 @@ static void mtk_pericfg_init(struct device_node *node)
 	if (r)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
+
+	mtk_register_reset_controller(node, 2, 0x0);
 }
 
 #define MT8590_PLL_FMAX		(2000 * MHZ)
-- 
1.9.1