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Message-ID: <4c931176-a09a-546c-d2b6-ea74028c78a2@cogentembedded.com>
Date: Sun, 21 Aug 2016 00:30:27 +0300
From: Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
To: Randy Li <ayaka@...lik.info>, linux-usb@...r.kernel.org
Cc: johnyoun@...opsys.com, gregkh@...uxfoundation.org,
robh+dt@...nel.org, mark.rutland@....com,
devicetree@...r.kernel.org, eddie.cai@...k-chips.com,
randy.li@...k-chips.com, kishon@...com,
linux-kernel@...r.kernel.org, heiko@...ech.de
Subject: Re: [PATCH 3/4] usb: dwc2: assert phy reset when waking up in rk3288
platform
Hello.
On 08/20/2016 11:32 PM, Randy Li wrote:
> On the rk3288 USB host-only port (the one that's not the OTG-enabled
> port) the PHY can get into a bad state when a wakeup is asserted (not
> just a wakeup from full system suspend but also a wakeup from
> autosuspend).
>
> We can get the PHY out of its bad state by asserting its "port reset",
> but unfortunately that seems to assert a reset onto the USB bus so it
> could confuse things if we don't actually deenumerate / reenumerate the
> device.
>
> We can also get the PHY out of its bad state by fully resetting it using
> the reset from the CRU (clock reset unit) in chip, which does a more full
> reset. The CRU-based reset appears to actually cause devices on the bus
> to be removed and reinserted, which fixes the problem (albeit in a hacky
> way).
>
> It's unfortunate that we need to do a full re-enumeration of devices at
> wakeup time, but this is better than alternative of letting the bus get
> wedged.
>
> The original patches came from Doug Anderson <dianders@...omium.org>.
>
> Signed-off-by: Randy Li <ayaka@...lik.info>
> ---
> drivers/usb/dwc2/core_intr.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
> index d85c5c9..c31c3fe 100644
> --- a/drivers/usb/dwc2/core_intr.c
> +++ b/drivers/usb/dwc2/core_intr.c
[...]
> @@ -379,6 +380,14 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
> /* Restart the Phy Clock */
> pcgcctl &= ~PCGCTL_STOPPCLK;
> dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
> +
> + /* It is a quirk in Rockchip RK3288, causing by
> + * a hardware bug. This will propagate out and
> + * eventually we'll re-enumerate the device.
> + * Not great but the best we can do */
The preferred multi-line comment style is this:
/*
* bla
* bla
*/
Yours is close. :-)
[...]
MBR, Sergei
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