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Date: Mon, 22 Aug 2016 09:23:38 +0100 From: Marc Zyngier <marc.zyngier@....com> To: Thomas Gleixner <tglx@...utronix.de> Cc: Fabio Estevam <fabio.estevam@....com>, John Stultz <john.stultz@...aro.org>, Linus Walleij <linus.walleij@...aro.org>, Jon Hunter <jonathanh@...dia.com>, Sudeep Holla <sudeep.holla@....com>, Jason Cooper <jason@...edaemon.net>, David Daney <david.daney@...ium.com>, Lorenzo Pieralisi <lorenzo.pieralisi@....com>, <linux-kernel@...r.kernel.org> Subject: [PATCH 2/4] irqchip/gic: Allow self-SGIs for SMP on UP configurations On systems where a single CPU is present, the GIC may not support having SGIs delivered to a target list. In that case, we use the self-SGI mechanism to allow the interrupt to be delivered locally. Tested-by: Fabio Estevam <fabio.estevam@....com> Signed-off-by: Marc Zyngier <marc.zyngier@....com> --- drivers/irqchip/irq-gic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index c2cab57..390fac5 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -769,6 +769,13 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) int cpu; unsigned long flags, map = 0; + if (unlikely(nr_cpu_ids == 1)) { + /* Only one CPU? let's do a self-IPI... */ + writel_relaxed(2 << 24 | irq, + gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); + return; + } + raw_spin_lock_irqsave(&irq_controller_lock, flags); /* Convert our logical CPU mask into a physical one. */ -- 2.1.4
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