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Message-id: <1471855308-12791-1-git-send-email-cw00.choi@samsung.com>
Date: Mon, 22 Aug 2016 17:41:46 +0900
From: Chanwoo Choi <cw00.choi@...sung.com>
To: s.nawrocki@...sung.com, tomasz.figa@...il.com
Cc: mturquette@...libre.com, sboyd@...eaurora.org, kgene@...nel.org,
k.kozlowski@...sung.com, chanwoo@...nel.org,
linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Chanwoo Choi <cw00.choi@...sung.com>
Subject: [PATCH 0/2] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain
This patches add the clocks for CMU_CDREX (DRAM Express Controller)
that generates the clocks for DRAM and NoC (Network on Chip) bus clock.
[Result for clk_summary on exynos5422-odroidxu3 board]
fout_bpll 0 0 825000000 0 0
mout_bpll 0 0 825000000 0 0
mout_mclk_cdrex 0 0 825000000 0 0
dout_pclk_core_mem 0 0 206250000 0 0
dout_sclk_cdrex 0 0 825000000 0 0
dout_clk2x_phy0 0 0 825000000 0 0
dout_aclk_cdrex1 0 0 412500000 0 0
dout_pclk_cdrex 0 0 103125000 0 0
dout_cclk_drex0 0 0 412500000 0 0
Chanwoo Choi (2):
dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller)
clk: samsung: exynos5420: Add clocks for CMU_CDREX domain
drivers/clk/samsung/clk-exynos5420.c | 35 ++++++++++++++++++++++++++++++++++
include/dt-bindings/clock/exynos5420.h | 11 ++++++++++-
2 files changed, 45 insertions(+), 1 deletion(-)
--
1.9.1
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