linux-kernel - Re: [PATCH v2 2/2] arm64: dts: Fix broken architected timer interrupt trigger

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Message-ID: <57BAD359.30707@arm.com>
Date:   Mon, 22 Aug 2016 11:26:33 +0100
From:   Marc Zyngier <marc.zyngier@....com>
To:     arm@...nel.org
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Andrew Lunn <andrew@...n.ch>,
        Krzysztof Kozlowski <k.kozlowski@...sung.com>,
        Mark Rutland <marc.rutland@....com>,
        Liu Gang <Gang.Liu@....com>,
        Masahiro Yamada <yamada.masahiro@...ionext.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Kevin Hilman <khilman@...libre.com>,
        Hou Zhiqiang <B48286@...escale.com>,
        Michal Simek <michal.simek@...inx.com>,
        Jon Hunter <jonathanh@...dia.com>,
        Kukjin Kim <kgene@...nel.org>,
        bcm-kernel-feedback-list@...adcom.com,
        linux-arm-kernel@...ts.infradead.org,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        Jason Cooper <jason@...edaemon.net>,
        Ray Jui <rjui@...adcom.com>,
        Tirumalesh Chalamarla <tchalamarla@...ium.com>,
        linux-samsung-soc@...r.kernel.org, Yuan Yao <yao.yuan@....com>,
        Wenbin Song <Wenbin.Song@...escale.com>,
        Jan Glauber <jglauber@...ium.com>,
        Gregory Clement <gregory.clement@...e-electrons.com>,
        linux-amlogic@...ts.infradead.org,
        Mingkai Hu <Mingkai.Hu@...escale.com>,
        soren.brinkmann@...inx.com,
        Rajesh Bhagat <rajesh.bhagat@...escale.com>,
        Scott Branden <sbranden@...adcom.com>,
        Duc Dang <dhdang@....com>, linux-kernel@...r.kernel.org,
        Carlo Caione <carlo@...lessm.com>,
        Carlo Caione <carlo@...one.org>,
        Dinh Nguyen <dinguyen@...nsource.altera.com>
Subject: Re: [PATCH v2 2/2] arm64: dts: Fix broken architected timer interrupt
 trigger

Arnd, Olof,

On 01/08/16 10:54, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
> 
> A number of DTs are being remarkably creative, declaring the interrupt
> to be edge triggered. A quick look at the TRM for the corresponding ARM
> CPUs clearly shows that this is wrong, and I've corrected those.
> For non-ARM designs (and in the absence of a publicly available TRM),
> I've made them active low as well, which can't be completely wrong
> as the GIC cannot disinguish between level low and level high.
> 
> The respective maintainers are of course welcome to prove me wrong.
> 
> While I was at it, I took the liberty to fix a couple of related issue,
> such as some spurious affinity bits on ThunderX, and their complete
> absence on ls1043a (both of which seem to be related to copy-pasting
> from other DTs).
> 
> Acked-by: Duc Dang <dhdang@....com>
> Acked-by: Carlo Caione <carlo@...lessm.com>
> Acked-by: Michal Simek <michal.simek@...inx.com>
> Acked-by: Krzysztof Kozlowski <k.kozlowski@...sung.com>
> Acked-by: Dinh Nguyen <dinguyen@...nsource.altera.com>
> Signed-off-by: Marc Zyngier <marc.zyngier@....com>

Any update on this patch? We have a workaround merged already, but it'd
be good to have the DTS fixed as well.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...