linux-kernel - Re: [PATCH 1/2] PCI: rockchip: fix broken ASPM due to incorrect L1PwrOnSc/Val

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Message-ID: <20160825134144.GA11257@localhost>
Date:   Thu, 25 Aug 2016 08:41:44 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Shawn Lin <shawn.lin@...k-chips.com>
Cc:     Bjorn Helgaas <bhelgaas@...gle.com>,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-pci@...r.kernel.org, Brian Norris <briannorris@...omium.org>
Subject: Re: [PATCH 1/2] PCI: rockchip: fix broken ASPM due to incorrect
 L1PwrOnSc/Val

On Thu, Aug 25, 2016 at 04:03:34PM +0800, Shawn Lin wrote:
> This is a bug of controller found recently which makes the
> default values of L1PwrOnSc and L1PwrOnVal unreliable when
> enabling ASPM. We could work around this by reading L1 substate
> control 2 register and then write back the value again.
> 
> Signed-off-by: Shawn Lin <shawn.lin@...k-chips.com>

My pci/host-rockchip branch hasn't been merged anywhere, so I just folded
both these patches into the original commits.

> ---
> 
>  drivers/pci/host/pcie-rockchip.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index 1671d02..ed782b51 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -40,6 +40,7 @@
>  #define PCIE_CLIENT_BASE			0x0
>  #define PCIE_RC_CONFIG_NORMAL_BASE		0x800000
>  #define PCIE_RC_CONFIG_BASE			0xa00000
> +#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2	0x90c
>  #define PCIE_RC_CONFIG_LCSR			0xd0
>  #define  PCIE_RC_CONFIG_LCSR_LBMIE		BIT(10)
>  #define  PCIE_RC_CONFIG_LCSR_LABIE		BIT(11)
> @@ -477,6 +478,18 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
>  		return err;
>  	}
>  
> +	/*
> +	 * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2
> +	 * before enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
> +	 * reliable which makes the controller in broken state when
> +	 * enabling ASPM. This is a controller's bug we need to work
> +	 * around.
> +	 */
> +	status = pcie_read(port,  PCIE_RC_CONFIG_BASE +
> +				  PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> +	pcie_write(port, status,  PCIE_RC_CONFIG_BASE +
> +				  PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
> +
>  	/* Enable Gen1 training */
>  	pcie_write(port,
>  		   HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
> -- 
> 2.3.7
> 
>