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Date: Mon, 29 Aug 2016 02:30:50 +0530
From: Madhavan Srinivasan <maddy@...ux.vnet.ibm.com>
To: linux-kernel@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org
Cc: Madhavan Srinivasan <maddy@...ux.vnet.ibm.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...nel.org>,
Peter Zijlstra <peterz@...radead.org>,
Jiri Olsa <jolsa@...nel.org>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Stephane Eranian <eranian@...il.com>,
Russell King <linux@....linux.org.uk>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
Michael Ellerman <mpe@...erman.id.au>,
Sukadev Bhattiprolu <sukadev@...ux.vnet.ibm.com>
Subject: [PATCH 05/13] powerpc/perf: Define enums for perf_arch_regs registers
Patch creates a perf_event_powerpc_arch_regs enum and macros
to include some of the powerpc pmu registers.
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Ingo Molnar <mingo@...nel.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Jiri Olsa <jolsa@...nel.org>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>
Cc: Stephane Eranian <eranian@...il.com>
Cc: Russell King <linux@....linux.org.uk>
Cc: Catalin Marinas <catalin.marinas@....com>
Cc: Will Deacon <will.deacon@....com>
Cc: Benjamin Herrenschmidt <benh@...nel.crashing.org>
Cc: Michael Ellerman <mpe@...erman.id.au>
Cc: Sukadev Bhattiprolu <sukadev@...ux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@...ux.vnet.ibm.com>
---
arch/powerpc/include/uapi/asm/perf_regs.h | 38 ++++++++++++++++++++++++
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 39 +++++++++++++++++++++++++
2 files changed, 77 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/perf_regs.h b/arch/powerpc/include/uapi/asm/perf_regs.h
index 6a93209748a1..e8f5553a61d1 100644
--- a/arch/powerpc/include/uapi/asm/perf_regs.h
+++ b/arch/powerpc/include/uapi/asm/perf_regs.h
@@ -47,4 +47,42 @@ enum perf_event_powerpc_regs {
PERF_REG_POWERPC_DSISR,
PERF_REG_POWERPC_MAX,
};
+
+enum perf_event_powerpc_arch_regs {
+ PERF_ARCH_REG_POWERPC_PVR,
+ PERF_ARCH_REG_POWERPC_PMC1,
+ PERF_ARCH_REG_POWERPC_PMC2,
+ PERF_ARCH_REG_POWERPC_PMC3,
+ PERF_ARCH_REG_POWERPC_PMC4,
+ PERF_ARCH_REG_POWERPC_PMC5,
+ PERF_ARCH_REG_POWERPC_PMC6,
+ PERF_ARCH_REG_POWERPC_PMC7,
+ PERF_ARCH_REG_POWERPC_PMC8,
+ PERF_ARCH_REG_POWERPC_MMCR0,
+ PERF_ARCH_REG_POWERPC_MMCR1,
+ PERF_ARCH_REG_POWERPC_SIER,
+ PERF_ARCH_REG_POWERPC_SIAR,
+ PERF_ARCH_REG_POWERPC_SDAR,
+ PERF_ARCH_REG_POWERPC_MMCRA,
+ PERF_ARCH_REG_POWERPC_MMCR2,
+ PERF_ARCH_REG_POWERPC_MAX,
+};
+
+#define PERF_ARCH_REG_PVR (1ULL<<PERF_ARCH_REG_POWERPC_PVR)
+#define PERF_ARCH_REG_PMC1 (1ULL<<PERF_ARCH_REG_POWERPC_PMC1)
+#define PERF_ARCH_REG_PMC2 (1ULL<<PERF_ARCH_REG_POWERPC_PMC2)
+#define PERF_ARCH_REG_PMC3 (1ULL<<PERF_ARCH_REG_POWERPC_PMC3)
+#define PERF_ARCH_REG_PMC4 (1ULL<<PERF_ARCH_REG_POWERPC_PMC4)
+#define PERF_ARCH_REG_PMC5 (1ULL<<PERF_ARCH_REG_POWERPC_PMC5)
+#define PERF_ARCH_REG_PMC6 (1ULL<<PERF_ARCH_REG_POWERPC_PMC6)
+#define PERF_ARCH_REG_PMC7 (1ULL<<PERF_ARCH_REG_POWERPC_PMC7)
+#define PERF_ARCH_REG_PMC8 (1ULL<<PERF_ARCH_REG_POWERPC_PMC8)
+#define PERF_ARCH_REG_MMCR0 (1ULL<<PERF_ARCH_REG_POWERPC_MMCR0)
+#define PERF_ARCH_REG_MMCR1 (1ULL<<PERF_ARCH_REG_POWERPC_MMCR1)
+#define PERF_ARCH_REG_SIER (1ULL<<PERF_ARCH_REG_POWERPC_SIER)
+#define PERF_ARCH_REG_SIAR (1ULL<<PERF_ARCH_REG_POWERPC_SIAR)
+#define PERF_ARCH_REG_SDAR (1ULL<<PERF_ARCH_REG_POWERPC_SDAR)
+#define PERF_ARCH_REG_MMCRA (1ULL<<PERF_ARCH_REG_POWERPC_MMCRA)
+#define PERF_ARCH_REG_MMCR2 (1ULL<<PERF_ARCH_REG_POWERPC_MMCR2)
+
#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
diff --git a/tools/arch/powerpc/include/uapi/asm/perf_regs.h b/tools/arch/powerpc/include/uapi/asm/perf_regs.h
index 6a93209748a1..bf249a27aa36 100644
--- a/tools/arch/powerpc/include/uapi/asm/perf_regs.h
+++ b/tools/arch/powerpc/include/uapi/asm/perf_regs.h
@@ -47,4 +47,43 @@ enum perf_event_powerpc_regs {
PERF_REG_POWERPC_DSISR,
PERF_REG_POWERPC_MAX,
};
+
+enum perf_event_powerpc_arch_regs {
+ PERF_ARCH_REG_POWERPC_PVR,
+ PERF_ARCH_REG_POWERPC_PMC1,
+ PERF_ARCH_REG_POWERPC_PMC2,
+ PERF_ARCH_REG_POWERPC_PMC3,
+ PERF_ARCH_REG_POWERPC_PMC4,
+ PERF_ARCH_REG_POWERPC_PMC5,
+ PERF_ARCH_REG_POWERPC_PMC6,
+ PERF_ARCH_REG_POWERPC_PMC7,
+ PERF_ARCH_REG_POWERPC_PMC8,
+ PERF_ARCH_REG_POWERPC_MMCR0,
+ PERF_ARCH_REG_POWERPC_MMCR1,
+ PERF_ARCH_REG_POWERPC_SIER,
+ PERF_ARCH_REG_POWERPC_SIAR,
+ PERF_ARCH_REG_POWERPC_SDAR,
+ PERF_ARCH_REG_POWERPC_MMCRA,
+ PERF_ARCH_REG_POWERPC_MMCR2,
+ PERF_ARCH_REG_POWERPC_MAX,
+};
+
+#define PERF_ARCH_REG_PVR 1ULL<<PERF_ARCH_REG_POWERPC_PVR
+#define PERF_ARCH_REG_PMC1 1ULL<<PERF_ARCH_REG_POWERPC_PMC1
+#define PERF_ARCH_REG_PMC2 1ULL<<PERF_ARCH_REG_POWERPC_PMC2
+#define PERF_ARCH_REG_PMC3 1ULL<<PERF_ARCH_REG_POWERPC_PMC3
+#define PERF_ARCH_REG_PMC4 1ULL<<PERF_ARCH_REG_POWERPC_PMC4
+#define PERF_ARCH_REG_PMC5 1ULL<<PERF_ARCH_REG_POWERPC_PMC5
+#define PERF_ARCH_REG_PMC6 1ULL<<PERF_ARCH_REG_POWERPC_PMC6
+#define PERF_ARCH_REG_PMC7 1ULL<<PERF_ARCH_REG_POWERPC_PMC7
+#define PERF_ARCH_REG_PMC8 1ULL<<PERF_ARCH_REG_POWERPC_PMC8
+#define PERF_ARCH_REG_MMCR0 1ULL<<PERF_ARCH_REG_POWERPC_MMCR0
+#define PERF_ARCH_REG_MMCR1 1ULL<<PERF_ARCH_REG_POWERPC_MMCR1
+#define PERF_ARCH_REG_SIER 1ULL<<PERF_ARCH_REG_POWERPC_SIER
+#define PERF_ARCH_REG_SIAR 1ULL<<PERF_ARCH_REG_POWERPC_SIAR
+#define PERF_ARCH_REG_SDAR 1ULL<<PERF_ARCH_REG_POWERPC_SDAR
+#define PERF_ARCH_REG_MMCRA 1ULL<<PERF_ARCH_REG_POWERPC_MMCRA
+#define PERF_ARCH_REG_MMCR2 1ULL<<PERF_ARCH_REG_POWERPC_MMCR2
+
+
#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
--
2.7.4
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