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Message-ID: <1472473626-15398-14-git-send-email-gabriel.fernandez@st.com>
Date: Mon, 29 Aug 2016 14:27:05 +0200
From: <gabriel.fernandez@...com>
To: Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Srinivas Kandagatla <srinivas.kandagatla@...il.com>,
Patrice Chotard <patrice.chotard@...com>,
Russell King <linux@...linux.org.uk>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Olivier Bideau <olivier.bideau@...com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Andrzej Hajda <a.hajda@...sung.com>,
Pankaj Dev <pankaj.dev@...com>,
Dinh Nguyen <dinguyen@...nsource.altera.com>,
Arnd Bergmann <arnd@...db.de>,
Thierry Reding <treding@...dia.com>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <kernel@...inux.com>,
<linux-clk@...r.kernel.org>, Lee Jones <lee.jones@...aro.org>,
Peter Griffin <peter.griffin@...aro.org>,
<arnaud.pouliquen@...com>, <benjamin.gaignard@...com>,
<vincent.abriou@...com>, <gabriel.fernandez@...com>,
Gabriel Fernandez <gabriel.fernandez@...aro.org>
Subject: [PATCH v3 13/14] ARM: DT: STi: STiH407: clock configuration to address 720p and 1080p
From: Gabriel Fernandez <gabriel.fernandez@...com>
It is necessary to properly configure these clocks in order
to address 720p and 1080p HDMI resolution.
Signed-off-by: Vincent Abriou <vincent.abriou@...com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@...com>
Acked-by: Peter Griffin <peter.griffin@...aro.org>
---
arch/arm/boot/dts/stih407.dtsi | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index d60f0d8..291ffac 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -16,7 +16,10 @@
#size-cells = <1>;
assigned-clocks = <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+ <&clk_s_c0_flexgen CLK_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
<&clk_s_d2_flexgen CLK_PIX_GDP1>,
@@ -26,14 +29,21 @@
assigned-clock-parents = <0>,
<0>,
+ <0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_pll1 0>,
<&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>;
- assigned-clock-rates = <297000000>, <297000000>;
+ assigned-clock-rates = <297000000>,
+ <108000000>,
+ <0>,
+ <400000000>,
+ <400000000>;
ranges;
--
1.9.1
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