linux-kernel - Re: [PATCH 1/3] perf/x86/intel/bts: Fix confused ordering of PMU callbacks

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Message-ID: <87d1krljo8.fsf@ashishki-desk.ger.corp.intel.com>
Date:   Mon, 29 Aug 2016 17:43:51 +0300
From:   Alexander Shishkin <alexander.shishkin@...ux.intel.com>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     vince@...ter.net, Ingo Molnar <mingo@...hat.com>,
        linux-kernel@...r.kernel.org, eranian@...gle.com,
        Arnaldo Carvalho de Melo <acme@...radead.org>
Subject: Re: [PATCH 1/3] perf/x86/intel/bts: Fix confused ordering of PMU callbacks

Peter Zijlstra <peterz@...radead.org> writes:

> On Wed, Aug 24, 2016 at 05:15:54PM +0300, Alexander Shishkin wrote:
>> @@ -221,10 +245,13 @@ static void __bts_event_start(struct perf_event *event)
>>  
>>  	/*
>>  	 * local barrier to make sure that ds configuration made it
>> -	 * before we enable BTS
>> +	 * before we enable BTS and bts::state goes ACTIVE
>>  	 */
>>  	wmb();
>>  
>> +	/* INACTIVE/STOPPED -> ACTIVE */
>> +	WRITE_ONCE(bts->state, BTS_STATE_ACTIVE);
>> +
>>  	intel_pmu_enable_bts(config);
>>  
>>  }
>
> Alexander, were you going to post a new version of this patch without
> the barrier confusion?

Yes, only the testcase exploded again over the weekend, looking at it
again.

Regards,
--
Alex