linux-kernel - [PATCH 2/3] PCI: Xilinx NWL PCIe: Enabling all MSI interrupts using MSI mask.

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Date:   Tue, 30 Aug 2016 16:09:17 +0530
From:   Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
To:     <robh@...nel.org>, <bhelgaas@...gle.com>,
        <colin.king@...onical.com>, <soren.brinkmann@...inx.com>,
        <marc.zyngier@....com>, <michal.simek@...inx.com>, <arnd@...db.de>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <rgummal@...inx.com>, Bharat Kumar Gogada <bharatku@...inx.com>
Subject: [PATCH 2/3] PCI: Xilinx NWL PCIe: Enabling all MSI interrupts using MSI mask.

The current mask enables and allows only one MSI interrupt on each MSI line.
This change, enables all MSI interrupts, which will also support End Points
with multi MSI support.

Signed-off-by: Bharat Kumar Gogada <bharatku@...inx.com>
---
 drivers/pci/host/pcie-xilinx-nwl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index 86c1834..d8d43e6 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -120,8 +120,8 @@
 					MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
 
 /* MSI interrupt status mask bits */
-#define MSGF_MSI_SR_LO_MASK		BIT(0)
-#define MSGF_MSI_SR_HI_MASK		BIT(0)
+#define MSGF_MSI_SR_LO_MASK		GENMASK(31, 0)
+#define MSGF_MSI_SR_HI_MASK		GENMASK(31, 0)
 
 #define MSII_PRESENT			BIT(0)
 #define MSII_ENABLE			BIT(0)
-- 
2.1.1