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Message-ID: <CACPK8XdFTxyUSLphUPagH-u2A3Th8jcCGd6UML3noSehx11oTg@mail.gmail.com>
Date: Tue, 30 Aug 2016 15:34:11 +0930
From: Joel Stanley <joel@....id.au>
To: Andrew Jeffery <andrew@...id.au>
Cc: Linus Walleij <linus.walleij@...aro.org>,
Alexandre Courbot <gnurou@...il.com>,
Mark Rutland <mark.rutland@....com>,
Rob Herring <robh+dt@...nel.org>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
Jeremy Kerr <jk@...abs.org>, linux-gpio@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v2 7/8] pinctrl: Add pinctrl-aspeed-g5 driver
2016-08-19 22:14 GMT+09:30 Andrew Jeffery <andrew@...id.au>:
> A small subset of pins and functions are exposed. The selection of pins
> and functions is driven by the development of OpenBMC[1] on the
> AST2500 SoC, particularly around booting the IBM Witherspoon platform.
>
> [1] https://github.com/openbmc/docs
>
> Signed-off-by: Andrew Jeffery <andrew@...id.au>
As with the g4 driver, this looks good and works fine on the
ast2500evb and witherspoon boards.
Reviewed-by: Joel Stanley <joel@....id.au>
> ---
>
> Since v1:
>
> * Fix the RMII1 signal descriptor bit
> * Add a number of new mux function and pin definitions
> * Sort the pin, group and function arrays for sanity
> * Add SoC-specific compatible string
>
> drivers/pinctrl/aspeed/Kconfig | 8 +
> drivers/pinctrl/aspeed/Makefile | 1 +
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 808 +++++++++++++++++++++++++++++
> 3 files changed, 817 insertions(+)
> create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
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