linux-kernel - [PATCH 05/10] MIPS: pm-cps: Add P6600 implementation lightweight sync types

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Message-ID: <1472640279-26593-6-git-send-email-matt.redfearn@imgtec.com>
Date:   Wed, 31 Aug 2016 11:44:34 +0100
From:   Matt Redfearn <matt.redfearn@...tec.com>
To:     Ralf Baechle <ralf@...ux-mips.org>
CC:     <linux-mips@...ux-mips.org>,
        Matt Redfearn <matt.redfearn@...tec.com>,
        Adam Buchbinder <adam.buchbinder@...il.com>,
        Masahiro Yamada <yamada.masahiro@...ionext.com>,
        Kees Cook <keescook@...omium.org>,
        <linux-kernel@...r.kernel.org>,
        Markos Chandras <markos.chandras@...tec.com>,
        Paul Burton <paul.burton@...tec.com>
Subject: [PATCH 05/10] MIPS: pm-cps: Add P6600 implementation lightweight sync types

P6600 implements the same lightweight sync types as previous CPUs.

Signed-off-by: Matt Redfearn <matt.redfearn@...tec.com>
Reviewed-by: Paul Burton <paul.burton@...tec.com>
---

 arch/mips/kernel/pm-cps.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index c6b9ad2256f0..f8c8edd0a451 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -674,6 +674,7 @@ static int __init cps_pm_init(void)
 	case CPU_PROAPTIV:
 	case CPU_M5150:
 	case CPU_P5600:
+	case CPU_P6600:
 		stype_intervention = 0x2;
 		stype_memory = 0x3;
 		stype_ordering = 0x10;
-- 
2.7.4