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Message-Id: <1472786217-52214-4-git-send-email-finley.xiao@rock-chips.com>
Date: Thu, 1 Sep 2016 20:16:56 -0700
From: Finley Xiao <finley.xiao@...k-chips.com>
To: srinivas.kandagatla@...aro.org, maxime.ripard@...e-electrons.com,
robh+dt@...nel.org, mark.rutland@....com, heiko@...ech.de,
linux@...linux.org.uk, catalin.marinas@....com,
will.deacon@....com, dianders@...omium.org
Cc: linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, wxt@...k-chips.com,
zhengsq@...k-chips.com, jay.xu@...k-chips.com,
huangtao@...k-chips.com, tony.xie@...k-chips.com,
cl@...k-chips.com, Finley Xiao <finley.xiao@...k-chips.com>
Subject: [PATCH v5 3/4] arm64: dts: rockchip: add efuse0 device node for rk3399
Add a efuse0 node in the device tree for the ARM64 rk3399 SoC.
Signed-off-by: Finley Xiao <finley.xiao@...k-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index a6dd623..05b48e2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -721,6 +721,35 @@
status = "disabled";
};
+ efuse0: efuse@...90000 {
+ compatible = "rockchip,rk3399-efuse";
+ reg = <0x0 0xff690000 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE1024NS>;
+ clock-names = "pclk_efuse";
+
+ /* Data cells */
+ cpul_leakage: cpul-leakage {
+ reg = <0x1a 0x1>;
+ };
+ cpub_leakage: cpub-leakage {
+ reg = <0x17 0x1>;
+ };
+ gpu_leakage: gpu-leakage {
+ reg = <0x18 0x1>;
+ };
+ center_leakage: center-leakage {
+ reg = <0x19 0x1>;
+ };
+ logic_leakage: logic-leakage {
+ reg = <0x1b 0x1>;
+ };
+ wafer_info: wafer-info {
+ reg = <0x1c 0x1>;
+ };
+ };
+
pmucru: pmu-clock-controller@...50000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff750000 0x0 0x1000>;
--
2.7.4
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