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Message-ID: <tip-d1992996753132e2dafe955cccb2fb0714d3cfc4@git.kernel.org>
Date: Fri, 2 Sep 2016 12:37:11 -0700
From: tip-bot for Emanuel Czirai <tipbot@...or.com>
To: linux-tip-commits@...r.kernel.org
Cc: bp@...e.de, hpa@...or.com, icanrealizeum@...il.com,
mingo@...nel.org, tglx@...utronix.de, linux-kernel@...r.kernel.org,
yaowu@...gle.com
Subject: [tip:x86/urgent] x86/AMD: Apply erratum 665 on machines without a
BIOS fix
Commit-ID: d1992996753132e2dafe955cccb2fb0714d3cfc4
Gitweb: http://git.kernel.org/tip/d1992996753132e2dafe955cccb2fb0714d3cfc4
Author: Emanuel Czirai <icanrealizeum@...il.com>
AuthorDate: Fri, 2 Sep 2016 07:35:50 +0200
Committer: Thomas Gleixner <tglx@...utronix.de>
CommitDate: Fri, 2 Sep 2016 20:42:28 +0200
x86/AMD: Apply erratum 665 on machines without a BIOS fix
AMD F12h machines have an erratum which can cause DIV/IDIV to behave
unpredictably. The workaround is to set MSRC001_1029[31] but sometimes
there is no BIOS update containing that workaround so let's do it
ourselves unconditionally. It is simple enough.
[ Borislav: Wrote commit message. ]
Signed-off-by: Emanuel Czirai <icanrealizeum@...il.com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Cc: Yaowu Xu <yaowu@...gle.com>
Cc: stable@...r.kernel.org
Link: http://lkml.kernel.org/r/20160902053550.18097-1-bp@alien8.de
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
---
arch/x86/kernel/cpu/amd.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f5c69d8..b81fe2d 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -669,6 +669,17 @@ static void init_amd_gh(struct cpuinfo_x86 *c)
set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
}
+#define MSR_AMD64_DE_CFG 0xC0011029
+
+static void init_amd_ln(struct cpuinfo_x86 *c)
+{
+ /*
+ * Apply erratum 665 fix unconditionally so machines without a BIOS
+ * fix work.
+ */
+ msr_set_bit(MSR_AMD64_DE_CFG, 31);
+}
+
static void init_amd_bd(struct cpuinfo_x86 *c)
{
u64 value;
@@ -726,6 +737,7 @@ static void init_amd(struct cpuinfo_x86 *c)
case 6: init_amd_k7(c); break;
case 0xf: init_amd_k8(c); break;
case 0x10: init_amd_gh(c); break;
+ case 0x12: init_amd_ln(c); break;
case 0x15: init_amd_bd(c); break;
}
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