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Message-ID: <alpine.DEB.2.20.1609061749250.5647@nanos>
Date:   Tue, 6 Sep 2016 17:50:14 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Waiman Long <Waiman.Long@....com>
cc:     Ingo Molnar <mingo@...hat.com>, "H. Peter Anvin" <hpa@...or.com>,
        linux-kernel@...r.kernel.org, x86@...nel.org,
        Borislav Petkov <bp@...e.de>,
        Andy Lutomirski <luto@...nel.org>,
        Dave Hansen <dave.hansen@...el.com>,
        Prarit Bhargava <prarit@...hat.com>,
        Scott J Norton <scott.norton@....com>,
        Douglas Hatch <doug.hatch@....com>,
        Randy Wright <rwright@....com>
Subject: Re: [RESEND PATCH v6] x86/hpet: Reduce HPET counter read
 contention

On Tue, 6 Sep 2016, Waiman Long wrote:
> 
> This is done by using a combination word with a sequence number and
> a bit lock. The CPU that gets the bit lock will be responsible for
> reading the HPET counter and update the sequence number. The others
> will monitor the change in sequence number and grab the HPET counter
> value accordingly. This change is only enabled on SMP configuration.

That hardly matches the implementation.
 
Thanks,

	tglx

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