linux-kernel - Re: [PATCH v3 8/8] gpio: Add Aspeed driver

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Message-ID: <CACRpkdbXu7i1_wHuF-tMK6vxK-UFV_YihQzrGKC3EmCtbrMozA@mail.gmail.com>
Date:   Wed, 7 Sep 2016 16:59:17 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Andrew Jeffery <andrew@...id.au>
Cc:     Joel Stanley <joel@....id.au>,
        Alexandre Courbot <gnurou@...il.com>,
        Mark Rutland <mark.rutland@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Benjamin Herrenschmidt <benh@...nel.crashing.org>,
        Jeremy Kerr <jk@...abs.org>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        Alistair Popple <alistair@...ple.id.au>
Subject: Re: [PATCH v3 8/8] gpio: Add Aspeed driver

On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@...id.au> wrote:

> From: Joel Stanley <joel@....id.au>
>
> The Aspeed SoCs contain GPIOs banked by letter, where each bank contains
> 8 pins. The GPIO banks are then grouped in sets of four in the register
> layout.
>
> The implementation exposes multiple banks through the one driver and
> requests and releases pins via the pinctrl subsystem. The hardware
> supports generation of interrupts from all GPIO-capable pins.
>
> A number of hardware features are not yet supported: Configuration of
> interrupt direction (ARM or LPC), debouncing, and WDT reset tolerance
> for output ports.
>
> Signed-off-by: Joel Stanley <joel@....id.au>
> Signed-off-by: Alistair Popple <alistair@...ple.id.au>
> Signed-off-by: Jeremy Kerr <jk@...abs.org>
> Signed-off-by: Andrew Jeffery <andrew@...id.au>

Patch applied to the GPIO tree.

As there are no compile-time dependencies between the
pin control and GPIO drivers I choose to merge the pinctrl
stuff through the pinctrl tree and the GPIO stuff through the GPIO
tree.

Yours,
Linus Walleij