linux-kernel - Re: [PATCH v3 2/9] drivers: irqchip: Add STM32 external interrupts support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <d790a3fd-766a-36d3-7a05-40b3198777c6@st.com>
Date:   Mon, 5 Sep 2016 01:47:27 -0600
From:   Alexandre Torgue <alexandre.torgue@...com>
To:     Thomas Gleixner <tglx@...utronix.de>
CC:     Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <marc.zyngier@....com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Mark Rutland <mark.rutland@....com>,
        Rob Herring <robh+dt@...nel.org>, <linux-gpio@...r.kernel.org>,
        <arnd@...db.de>, <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        Daniel Thompson <daniel.thompson@...aro.org>,
        <bruherrera@...il.com>, <lee.jones@...aro.org>
Subject: Re: [PATCH v3 2/9] drivers: irqchip: Add STM32 external interrupts support

Hi Thomas,

On 09/02/2016 08:57 PM, Thomas Gleixner wrote:
> Alexandre,
>
> On Fri, 2 Sep 2016, Alexandre TORGUE wrote:
>
> This all looks very reasonable. The only complaint I have is your variable
> declaration ordering or the lack thereof.
>
> 1)
>> +	struct irq_domain *domain = irq_desc_get_handler_data(desc);
>> +	struct irq_chip_generic *gc = domain->gc->gc[0];
>> +	struct irq_chip *chip = irq_desc_get_chip(desc);
>> +	unsigned long pending;
>> +	int n;
>
> 2)
>> +	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
>> +	u32 rtsr, ftsr;
>> +	int pin = data->hwirq;
>
> 3)
>> +	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
>> +	int pin = data->hwirq;
>> +	u32 emr;
>
> 4)
>> +	irq_hw_number_t hwirq;
>> +	struct irq_fwspec *fwspec = data;
>> +	struct irq_chip_generic *gc = d->gc->gc[0];
>
> 5)
>> +	int nr_irqs, nr_exti, ret, i;
>> +	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
>> +	struct irq_domain *domain;
>> +	struct irq_chip_generic *gc;
>> +	void *base;
>
> #1 and 3 have the ordering which is preferred in the irq code.
>
> #2, #4 and #5 are three permutations which are way harder to read.
>
>> +	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
>> +	int pin = data->hwirq;
>> +	u32 rtsr, ftsr;
>
>> +	struct irq_chip_generic *gc = d->gc->gc[0];
>> +	struct irq_fwspec *fwspec = data;
>> +	irq_hw_number_t hwirq;
>
>> +	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
>> +	int nr_irqs, nr_exti, ret, i;
>> +	struct irq_chip_generic *gc;
>> +	struct irq_domain *domain;
>> +	void *base;
>
> Can you spot the difference?

Thanks for review and for proposal. It Will be in next version.

Regards

Alex

>
> Thanks,
>
> 	tglx
>



--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html