linux-kernel - [tip:x86/platform] x86/platform/intel-mid: Add Intel Penwell to ID table

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Message-ID: <tip-8e522e1d321b12829960c9b26668c92f14c68d7f@git.kernel.org>
Date:   Thu, 8 Sep 2016 06:19:26 -0700
From:   tip-bot for Andy Shevchenko <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     torvalds@...ux-foundation.org, linux-kernel@...r.kernel.org,
        mingo@...nel.org, hpa@...or.com, andriy.shevchenko@...ux.intel.com,
        tglx@...utronix.de, peterz@...radead.org
Subject: [tip:x86/platform] x86/platform/intel-mid: Add Intel Penwell to ID
 table

Commit-ID:  8e522e1d321b12829960c9b26668c92f14c68d7f
Gitweb:     http://git.kernel.org/tip/8e522e1d321b12829960c9b26668c92f14c68d7f
Author:     Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
AuthorDate: Thu, 8 Sep 2016 13:32:31 +0300
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Thu, 8 Sep 2016 14:07:53 +0200

x86/platform/intel-mid: Add Intel Penwell to ID table

Commit:

  ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")

... enabled the PWRMU driver on platforms based on Intel Penwell, but
unfortunately this is not enough.

Add Intel Penwell ID to pci-mid.c driver as well. To avoid confusion in the
future add a comment to both drivers.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Fixes: ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")
Link: http://lkml.kernel.org/r/20160908103232.137587-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/platform/intel-mid/pwr.c | 1 +
 drivers/pci/pci-mid.c             | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c
index 2dfe998..146ed54 100644
--- a/arch/x86/platform/intel-mid/pwr.c
+++ b/arch/x86/platform/intel-mid/pwr.c
@@ -427,6 +427,7 @@ static const struct mid_pwr_device_info mid_info = {
 	.set_initial_state = mid_set_initial_state,
 };
 
+/* This table should be in sync with the one in drivers/pci/pci-mid.c */
 static const struct pci_device_id mid_pwr_pci_ids[] = {
 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
diff --git a/drivers/pci/pci-mid.c b/drivers/pci/pci-mid.c
index b7ea64f..55f453d 100644
--- a/drivers/pci/pci-mid.c
+++ b/drivers/pci/pci-mid.c
@@ -60,7 +60,12 @@ static struct pci_platform_pm_ops mid_pci_platform_pm = {
 
 #define ICPU(model)	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 
+/*
+ * This table should be in sync with the one in
+ * arch/x86/platform/intel-mid/pwr.c.
+ */
 static const struct x86_cpu_id lpss_cpu_ids[] = {
+	ICPU(INTEL_FAM6_ATOM_PENWELL),
 	ICPU(INTEL_FAM6_ATOM_MERRIFIELD),
 	{}
 };