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Message-ID: <1473343836.1896.17.camel@mtkswgap22>
Date: Thu, 8 Sep 2016 22:10:36 +0800
From: Mars Cheng <mars.cheng@...iatek.com>
To: Marc Zyngier <marc.zyngier@....com>
CC: Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
"Michael Turquette" <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Erin Lo <erin.lo@...iatek.com>,
James Liao <jamesjj.liao@...iatek.com>,
<linux-clk@...r.kernel.org>, CC Hwang <cc.hwang@...iatek.com>,
Loda Choui <loda.chou@...iatek.com>,
Miles Chen <miles.chen@...iatek.com>,
Scott Shu <scott.shu@...iatek.com>,
Jades Shih <jades.shih@...iatek.com>,
"Yingjoe Chen" <yingjoe.chen@...iatek.com>,
My Chuang <my.chuang@...iatek.com>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<wsd_upstream@...iatek.com>
Subject: Re: [PATCH 3/4] arm64: dts: mediatek: add mt6797 support
On Thu, 2016-09-08 at 14:15 +0100, Marc Zyngier wrote:
> On 08/09/16 11:49, Mars Cheng wrote:
> > This adds basic chip support for MT6797 SoC.
> >
> > Signed-off-by: Mars Cheng <mars.cheng@...iatek.com>
> > ---
[...]
>
> > + gic: interrupt-controller@...00000 {
> > + compatible = "arm,gic-v3";
> > + #interrupt-cells = <3>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-controller;
> > + reg = <0 0x19000000 0 0x10000>, /* GICD */
> > + <0 0x19200000 0 0x200000>, /* GICR */
> > + <0 0x10240000 0 0x2000>; /* GICC */
>
> Where are the GICV and GICH regions? No ITS?
Have confirmed with our HW guys, there is no GICV, GICH, nor ITS in our
GIC design.
Thanks.
>
> Thanks,
>
> M.
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