linux-kernel - RE: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation detection

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <3E5A0FA7E9CA944F9D5414FEC6C712205DFEDD34@ORSMSX106.amr.corp.intel.com>
Date:   Thu, 8 Sep 2016 16:53:52 +0000
From:   "Yu, Fenghua" <fenghua.yu@...el.com>
To:     Borislav Petkov <bp@...e.de>
CC:     Thomas Gleixner <tglx@...utronix.de>,
        "Anvin, H Peter" <h.peter.anvin@...el.com>,
        Ingo Molnar <mingo@...e.hu>,
        "Luck, Tony" <tony.luck@...el.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Tejun Heo <tj@...nel.org>,
        Stephane Eranian <eranian@...gle.com>,
        Marcelo Tosatti <mtosatti@...hat.com>,
        David Carrillo-Cisneros <davidcc@...gle.com>,
        Shaohua Li <shli@...com>,
        "Shankar, Ravi V" <ravi.v.shankar@...el.com>,
        Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
        "Prakhya, Sai Praneeth" <sai.praneeth.prakhya@...el.com>,
        linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: RE: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache
 Allocation detection

> From: Borislav Petkov [mailto:bp@...e.de]
> On Thu, Sep 08, 2016 at 02:57:01AM -0700, Fenghua Yu wrote:
> > From: Vikas Shivappa <vikas.shivappa@...ux.intel.com>
> >
> > This patch includes CPUID enumeration routines for Cache allocation
> > and new values to track resources to the cpuinfo_x86 structure.
> >
> > Cache allocation provides a way for the Software (OS/VMM) to restrict
> > cache allocation to a defined 'subset' of cache which may be
> > overlapping with other 'subsets'. This feature is used when allocating
> > a line in cache ie when pulling new data into the cache. The
> > programming of the hardware is done via programming MSRs (model
> specific registers).
> >
> > Signed-off-by: Vikas Shivappa <vikas.shivappa@...ux.intel.com>
> > Signed-off-by: Fenghua Yu <fenghua.yu@...el.com>
> > Reviewed-by: Tony Luck <tony.luck@...el.com>
> > ---
> 
> ...
> 
> > diff --git a/arch/x86/include/asm/cpufeatures.h
> > b/arch/x86/include/asm/cpufeatures.h
> > index 92a8308..62d979b9 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -12,7 +12,7 @@
> >  /*
> >   * Defines x86 CPU feature bits
> >   */
> > -#define NCAPINTS	18	/* N 32-bit words worth of info */
> > +#define NCAPINTS	19	/* N 32-bit words worth of info */
> >  #define NBUGINTS	1	/* N 32-bit bug flags */
> >
> >  /*
> > @@ -220,6 +220,7 @@
> >  #define X86_FEATURE_RTM		( 9*32+11) /* Restricted Transactional
> Memory */
> >  #define X86_FEATURE_CQM		( 9*32+12) /* Cache QoS Monitoring
> */
> >  #define X86_FEATURE_MPX		( 9*32+14) /* Memory Protection
> Extension */
> > +#define X86_FEATURE_RDT		( 9*32+15) /* Resource Director
> Technology */
> >  #define X86_FEATURE_AVX512F	( 9*32+16) /* AVX-512 Foundation */
> >  #define X86_FEATURE_AVX512DQ	( 9*32+17) /* AVX-512 DQ
> (Double/Quad granular) Instructions */
> >  #define X86_FEATURE_RDSEED	( 9*32+18) /* The RDSEED instruction
> */
> > @@ -286,6 +287,9 @@
> >  #define X86_FEATURE_SUCCOR	(17*32+1) /* Uncorrectable error
> containment and recovery */
> >  #define X86_FEATURE_SMCA	(17*32+3) /* Scalable MCA */
> >
> > +/* Intel-defined CPU features, CPUID level 0x00000010:0 (ebx), word
> > +18 */
> 
> Seems like this leaf is dedicated to CAT and has only 2 feature bits defined in
> the SDM. Please use init_scattered_cpuid_features() instead of adding a
> whole CAP word.

Actually this leaf will be extended to have more bits for more resources allocation.

Thanks.

-Fenghua