linux-kernel - [PATCH v5 5/5] dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC

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Message-Id: <1473703967-21356-6-git-send-email-jorik@kippendief.biz>
Date:   Mon, 12 Sep 2016 20:12:47 +0200
From:   jorik@...pendief.biz
To:     wens@...e.org, maxime.ripard@...e-electrons.com
Cc:     mark.rutland@....com, robh+dt@...nel.org, linux@...linux.org.uk,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, Jorik Jonker <jorik@...pendief.biz>
Subject: [PATCH v5 5/5] dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC

From: Jorik Jonker <jorik@...pendief.biz>

These peripherals can only be muxed to these pins, so they are
associated in the DTSI instead of the board files. This makes it very
easy to enable them using overlays or u-boot commands:

 => fdt set /soc/i2c@...2ac00 status okay

Signed-off-by: Jorik Jonker <jorik@...pendief.biz>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index ed6628d..bfc9200 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -483,6 +483,45 @@
 			status = "disabled";
 		};
 
+		i2c0: i2c@...2ac00 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@...2b000 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C1>;
+			resets = <&ccu RST_BUS_I2C1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@...2b400 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C2>;
+			resets = <&ccu RST_BUS_I2C2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		gic: interrupt-controller@...81000 {
 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 			reg = <0x01c81000 0x1000>,
-- 
2.7.4