linux-kernel - [tip:ras/core] x86/mce/AMD: Use msr_ops.misc() in allocate_threshold

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Message-ID: <tip-74ab0e7a836a7df772af50cac21267eb43688841@git.kernel.org>
Date:   Tue, 13 Sep 2016 06:28:07 -0700
From:   tip-bot for Yazen Ghannam <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     tglx@...utronix.de, hpa@...or.com, mingo@...nel.org,
        linux-kernel@...r.kernel.org, Yazen.Ghannam@....com, bp@...e.de
Subject: [tip:ras/core] x86/mce/AMD: Use msr_ops.misc() in
 allocate_threshold_blocks()

Commit-ID:  74ab0e7a836a7df772af50cac21267eb43688841
Gitweb:     http://git.kernel.org/tip/74ab0e7a836a7df772af50cac21267eb43688841
Author:     Yazen Ghannam <Yazen.Ghannam@....com>
AuthorDate: Mon, 12 Sep 2016 09:59:27 +0200
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Tue, 13 Sep 2016 15:23:06 +0200

x86/mce/AMD: Use msr_ops.misc() in allocate_threshold_blocks()

Change MSR_IA32_MCx_MISC() macro to msr_ops.misc() because SMCA machines
define a different set of MSRs and msr_ops will give you the correct
MISC register.

Signed-off-by: Yazen Ghannam <Yazen.Ghannam@....com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Link: http://lkml.kernel.org/r/1468269447-8808-1-git-send-email-Yazen.Ghannam@amd.com
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>

---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 7b7f3be..78b7681 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -869,7 +869,7 @@ static int threshold_create_bank(unsigned int cpu, unsigned int bank)
 		}
 	}
 
-	err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank));
+	err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank));
 	if (!err)
 		goto out;