linux-kernel - [tip:ras/core] x86/mce/AMD: Ensure the deferred error interrupt is of type APIC on SMCA systems

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Message-ID: <tip-66ef269dbbe45e264ccf7146d5db32b04478d148@git.kernel.org>
Date:   Tue, 13 Sep 2016 06:31:52 -0700
From:   tip-bot for Yazen Ghannam <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     tglx@...utronix.de, Yazen.Ghannam@....com, hpa@...or.com,
        mingo@...nel.org, bp@...e.de, linux-kernel@...r.kernel.org
Subject: [tip:ras/core] x86/mce/AMD: Ensure the deferred error interrupt is
 of type APIC on SMCA systems

Commit-ID:  66ef269dbbe45e264ccf7146d5db32b04478d148
Gitweb:     http://git.kernel.org/tip/66ef269dbbe45e264ccf7146d5db32b04478d148
Author:     Yazen Ghannam <Yazen.Ghannam@....com>
AuthorDate: Mon, 12 Sep 2016 09:59:36 +0200
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Tue, 13 Sep 2016 15:23:11 +0200

x86/mce/AMD: Ensure the deferred error interrupt is of type APIC on SMCA systems

The Deferred Error Interrupt Type is set per bank on Scalable MCA
systems. This is done in a bitfield in the MCA_CONFIG register of each
bank. We should set its type to APIC-based interrupt and not assume BIOS
has set it for us.

Signed-off-by: Yazen Ghannam <Yazen.Ghannam@....com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Link: http://lkml.kernel.org/r/1472737486-1720-1-git-send-email-Yazen.Ghannam@amd.com
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>

---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 0f9d078..16766e0 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -463,6 +463,20 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 		 */
 		smca_high &= ~BIT(2);
 
+		/*
+		 * SMCA sets the Deferred Error Interrupt type per bank.
+		 *
+		 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
+		 * if the DeferredIntType bit field is available.
+		 *
+		 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
+		 * high portion of the MSR). OS should set this to 0x1 to enable
+		 * APIC based interrupt. First, check that no interrupt has been
+		 * set.
+		 */
+		if ((smca_low & BIT(5)) && !((smca_high >> 5) & 0x3))
+			smca_high |= BIT(5);
+
 		wrmsr(smca_addr, smca_low, smca_high);
 	}