linux-kernel - Re: [PATCH 2/2] usb: dwc3: Added a property to set GFLADJ register

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <39809403-0b2b-09d9-452d-9689505ecff7@synopsys.com>
Date:   Tue, 13 Sep 2016 12:12:00 -0700
From:   John Youn <John.Youn@...opsys.com>
To:     Rob Herring <robh@...nel.org>, John Youn <John.Youn@...opsys.com>
CC:     Felipe Balbi <balbi@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Mark Rutland <mark.rutland@....com>,
        "Thinh Nguyen" <Thinh.Nguyen@...opsys.com>
Subject: Re: [PATCH 2/2] usb: dwc3: Added a property to set GFLADJ register

On 9/12/2016 8:30 AM, Rob Herring wrote:
> On Thu, Sep 01, 2016 at 02:32:33PM -0700, John Youn wrote:
>> From: Thinh Nguyen <thinhn@...opsys.com>
>>
>> Added gfladj variable to control the core behavior with respect to
>> SOF, ITP, and frame timer functionality.
>>
>> Currently there is dwc->fladj that holds a single field in GFLADJ
>> register (GFLADJ.GFLADJ_30MHZ). A new variable gfladj is added to
>> dwc structure to allow setting of the entire GFLADJ register. If
>> dwc->gfladj is set, then it has a higher priority than dwc->fladj
>> when writing to the GFLADJ register.
> 
> I'm not a fan of magic register values for DT properties.
> 

Sure. Felipe gave the same feedback. We'll fix it.

> How many fields in this register that you will ever need to touch?
> 
>> Synopsys HW setup (HAPS DX and phy board) requires a preset to this
>> register to improve interoperablitity. For example, the value for
>> GFLADJ_REFCLK_LPM_SEL should be set to 0 with ref_clk period of 50.
> 
> This sounds like it should be handled in the driver. Is it a simple, 
> constant correlation of ref_clk period to this value?

I don't know. I'll look into it.

Regards,
John