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Message-ID: <878tuwl5bq.fsf@linux.intel.com>
Date: Tue, 13 Sep 2016 08:46:49 +0300
From: Felipe Balbi <balbi@...nel.org>
To: Rob Herring <robh@...nel.org>, John Youn <johnyoun@...opsys.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-usb@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Mark Rutland <mark.rutland@....com>,
Thinh Nguyen <thinhn@...opsys.com>
Subject: Re: [PATCH 2/2] usb: dwc3: Added a property to set GFLADJ register
Hi,
Rob Herring <robh@...nel.org> writes:
>> Synopsys HW setup (HAPS DX and phy board) requires a preset to this
>> register to improve interoperablitity. For example, the value for
>> GFLADJ_REFCLK_LPM_SEL should be set to 0 with ref_clk period of 50.
>
> This sounds like it should be handled in the driver. Is it a simple,
> constant correlation of ref_clk period to this value?
you mean that this could be calculated based off of clk_get_rate() ?
--
balbi
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