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Message-ID: <1473839072-5673-9-git-send-email-kishon@ti.com>
Date: Wed, 14 Sep 2016 13:13:49 +0530
From: Kishon Vijay Abraham I <kishon@...com>
To: <gregkh@...uxfoundation.org>
CC: <kishon@...com>, <linux-kernel@...r.kernel.org>
Subject: [PATCH 08/51] Documentation: bindings: add dt documentation for Rockchip PCIe PHY
From: Shawn Lin <shawn.lin@...k-chips.com>
This patch adds a binding that describes the Rockchip PCIe PHY found
on Rockchip SoCs PCIe interface.
Signed-off-by: Shawn Lin <shawn.lin@...k-chips.com>
Acked-by: Rob Herring <robh@...nel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
---
.../devicetree/bindings/phy/rockchip-pcie-phy.txt | 31 ++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
new file mode 100644
index 0000000..0f6222a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
@@ -0,0 +1,31 @@
+Rockchip PCIE PHY
+-----------------------
+
+Required properties:
+ - compatible: rockchip,rk3399-pcie-phy
+ - #phy-cells: must be 0
+ - clocks: Must contain an entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+ - clock-names: Must be "refclk"
+ - resets: Must contain an entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names: Must be "phy"
+
+Example:
+
+grf: syscon@...70000 {
+ compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ...
+
+ pcie_phy: pcie-phy {
+ compatible = "rockchip,rk3399-pcie-phy";
+ #phy-cells = <0>;
+ clocks = <&cru SCLK_PCIEPHY_REF>;
+ clock-names = "refclk";
+ resets = <&cru SRST_PCIEPHY>;
+ reset-names = "phy";
+ };
+};
--
1.7.9.5
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