lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Date:   Tue, 20 Sep 2016 15:15:20 +0300
From:   Mika Westerberg <mika.westerberg@...ux.intel.com>
To:     Linus Walleij <linus.walleij@...aro.org>
Cc:     Marc Zyngier <marc.zyngier@....com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Phidias Chiang <phidias.chiang@...onical.com>,
        Anisse Astier <anisse@...ier.eu>,
        Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
        Yu C Chen <yu.c.chen@...el.com>,
        Mika Westerberg <mika.westerberg@...ux.intel.com>,
        linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH v3 0/3] gpio / pinctrl: cherryview: Fix missing events from EC

Hi,

Up until now systems having Intel Cherryview/Braswell might lose GPEs
(General Purpose Events) from EC (Embedded Controller) because the pinctrl
driver masks all interrupt sources at probe time. I tried to fix this
already in bcb48cca23ec ("pinctrl: cherryview: Do not mask all interrupts
in probe") but it resulted that the irq core masked all the interrupts
because now we pass handle_bad_irq() as default handler for the irqchip.

After reading again the hardware spec, I think I finally understand the
problem correctly. In summary for southwest and north communities only the
first 8 (or 16) wires can be used to generate interrupts. Rest are reserved
for GPEs.

We fix this by excluding these only GPE capable wires from the IRQ domain
of the gpiochip.

This first follows what LinusW suggested and adds irq_valid_mask for each
gpiochip and then converts pinctrl-cherryview to use it.

Previous version of the patches and the discussion around this issue can be
found here:

  v2: http://www.spinics.net/lists/linux-gpio/msg16760.html
  v1: https://lkml.org/lkml/2015/5/22/111

Changes from v2:
  - Add irq_need_valid_mask flag that if set will make gpiochip_add_data()
    allocate irq_valid_mask for the chip.
  - Drop gpiochip_irqchip_exclude_irq() in favor of directly using
    set_/clear_bit() in drivers.
  - Use likely() annotation in gpiochip_irqchip_irq_valid().
  - Changed ordering of last two patches because there is no dependency
    anymore.

Changes from v1:
  - Only allocate irq_valid_mask when needed
  - Provide gpiochip_irqchip_exclude_irq() helper which allows drivers to
    select which GPIOs to exclude.
  - Use ->nrirqs in chv_gpio_irq_handler()
  - Added patch to convert the driver to use devm_gpiochip_add_data() so
    we can just return if gpiochip_irqchip_exclude_irq() fails (and also
    this simplifies the driver).

Mika Westerberg (3):
  gpiolib: Make it possible to exclude GPIOs from IRQ domain
  pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domain
  pinctrl: cherryview: Convert to use devm_gpiochip_add_data()

 Documentation/gpio/driver.txt              |  6 +++
 drivers/gpio/gpiolib.c                     | 66 ++++++++++++++++++++++++++++--
 drivers/pinctrl/intel/pinctrl-cherryview.c | 55 ++++++++++++++++---------
 include/linux/gpio/driver.h                |  6 +++
 4 files changed, 111 insertions(+), 22 deletions(-)

-- 
2.9.3

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ