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Message-Id: <20160922174052.780983456@linuxfoundation.org>
Date: Thu, 22 Sep 2016 19:40:29 +0200
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
stable@...r.kernel.org, Caesar Wang <wxt@...k-chips.com>,
Heiko Stuebner <heiko@...ech.de>,
Jonathan Cameron <jic23@...nel.org>
Subject: [PATCH 4.7 095/184] arm: dts: rockchip: add reset node for the exist saradc SoCs
4.7-stable review patch. If anyone has any objections, please let me know.
------------------
From: Caesar Wang <wxt@...k-chips.com>
commit 3d4267a5a3a4b7619b80ad1839d8b3bedd8b7a8d upstream.
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: Caesar Wang <wxt@...k-chips.com>
Acked-by: Heiko Stuebner <heiko@...ech.de>
Signed-off-by: Jonathan Cameron <jic23@...nel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
arch/arm/boot/dts/rk3066a.dtsi | 2 ++
arch/arm/boot/dts/rk3288.dtsi | 2 ++
arch/arm/boot/dts/rk3xxx.dtsi | 2 ++
3 files changed, 6 insertions(+)
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -197,6 +197,8 @@
clock-names = "saradc", "apb_pclk";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
status = "disabled";
};
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -279,6 +279,8 @@
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
status = "disabled";
};
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -399,6 +399,8 @@
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
status = "disabled";
};
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