linux-kernel - Re: [PATCH] drm: tilcdc: add a workaround for failed clk_set

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Message-ID: <dd67b1e8-0ab1-b6a9-61a1-4da2b40f1ef5@ti.com>
Date:   Wed, 28 Sep 2016 13:57:55 +0300
From:   Jyri Sarha <jsarha@...com>
To:     Bartosz Golaszewski <bgolaszewski@...libre.com>,
        Tomi Valkeinen <tomi.valkeinen@...com>,
        David Airlie <airlied@...ux.ie>,
        Kevin Hilman <khilman@...libre.com>,
        Michael Turquette <mturquette@...libre.com>
CC:     linux-drm <dri-devel@...ts.freedesktop.org>,
        LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm: tilcdc: add a workaround for failed clk_set_rate()

On 09/27/16 18:29, Bartosz Golaszewski wrote:
> Some architectures don't use the common clock framework and don't
> implement all the clk interfaces for every clock. This is the case
> for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1.
> 
> Trying to set the clock rate for the LCDC clock results in -EINVAL
> being returned.
> 
> As a workaround for that: if the call to clk_set_rate() fails, fall
> back to adjusting the clock divider instead. Proper divider value is
> calculated by dividing the current clock rate by the required pixel
> clock rate in HZ.
> 
> This code is based on a hack initially developed internally for
> baylibre by Karl Beldan <kbeldan@...libre.com>.
> 
> Tested with a da850-lcdk with an LCD display connected over VGA.
> 

Could you rebase the fix on top of latest drm-next[1] (or my latest pull
request tag[2])?

The conflict is so big that it is better the check that the fix still
works after rebasing.

Best regards,
Jyri

[1] git://people.freedesktop.org/~airlied/linux drm-next
[2] https://github.com/jsarha/linux tags/tilcdc-4.9-3.1

> Signed-off-by: Bartosz Golaszewski <bgolaszewski@...libre.com>
> ---
>  drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 31 ++++++++++++++++++++++++-------
>  1 file changed, 24 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> index 2087689..f2ff3b1 100644
> --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> @@ -636,22 +636,40 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
>  	struct drm_device *dev = crtc->dev;
>  	struct tilcdc_drm_private *priv = dev->dev_private;
>  	unsigned long lcd_clk;
> -	const unsigned clkdiv = 2; /* using a fixed divider of 2 */
> +	unsigned int clkdiv;
>  	int ret;
>  
>  	pm_runtime_get_sync(dev->dev);
>  
>  	tilcdc_crtc_disable(crtc);
>  
> +	clkdiv = 2; /* first try using a standard divider of 2 */
> +
>  	/* mode.clock is in KHz, set_rate wants parameter in Hz */
>  	ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
> +	lcd_clk = clk_get_rate(priv->clk);
>  	if (ret < 0) {
> -		dev_err(dev->dev, "failed to set display clock rate to: %d\n",
> -				crtc->mode.clock);
> -		goto out;
> -	}
> +		/*
> +		 * If we fail to set the clock rate (some architectures don't
> +		 * use the common clock framework yet and may not implement
> +		 * all the clk API calls for every clock), try the next best
> +		 * thing: adjusting the clock divider, unless clk_get_rate()
> +		 * failed as well.
> +		 */
> +		dev_err(dev->dev,
> +			"failed to set display clock rate to: %d\n",
> +			crtc->mode.clock);
> +		if (!lcd_clk) {
> +			/* Nothing more we can do. Just bail out. */
> +			dev_err(dev->dev,
> +				"failed to read the display clock rate\n");
> +			goto out;
> +		}
>  
> -	lcd_clk = clk_get_rate(priv->clk);
> +		dev_info(dev->dev,
> +			 "falling back to adjusting the clock divisor\n");
> +		clkdiv = DIV_ROUND_CLOSEST(lcd_clk, (crtc->mode.clock * 1000));
> +	}
>  
>  	DBG("lcd_clk=%lu, mode clock=%d, div=%u",
>  		lcd_clk, crtc->mode.clock, clkdiv);
> @@ -664,7 +682,6 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
>  		tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
>  				LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
>  				LCDC_V2_CORE_CLK_EN);
> -
>  	if (tilcdc_crtc_is_on(crtc))
>  		tilcdc_crtc_enable(crtc);
>  
>