linux-kernel - Re: [PATCH locking/Documentation 1/2] Add note of release-acquire store vulnerability

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Message-Id: <20160930113531.GN14933@linux.vnet.ibm.com>
Date:   Fri, 30 Sep 2016 04:35:31 -0700
From:   "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
To:     Will Deacon <will.deacon@....com>
Cc:     Boqun Feng <boqun.feng@...il.com>,
        Peter Zijlstra <peterz@...radead.org>,
        linux-kernel@...r.kernel.org, mingo@...nel.org,
        dhowells@...hat.com, stern@...land.harvard.edu
Subject: Re: [PATCH locking/Documentation 1/2] Add note of release-acquire
 store vulnerability

On Fri, Sep 30, 2016 at 10:20:09AM +0100, Will Deacon wrote:
> On Fri, Sep 30, 2016 at 01:53:52PM +0800, Boqun Feng wrote:
> > On Thu, Sep 29, 2016 at 10:23:22AM -0700, Paul E. McKenney wrote:
> > > If two processes are related by a RELEASE+ACQUIRE pair, ordering can be
> > > broken if a third process overwrites the value written by the RELEASE
> > > operation before the ACQUIRE operation has a chance of reading it, for
> > > example:
> > > 
> > > 	P0(int *x, int *y)
> > > 	{
> > > 		WRITE_ONCE(*x, 1);
> > > 		smp_wmb();
> >                ^^^^^^^^^^^
> > 
> > What is this smp_wmb() for?

Seems redundant to me, now that you mention it.  ;-)

But maybe this does something on ARM?

> > > 		smp_store_release(y, 1);
> > > 	}
> > > 
> > > 	P1(int *y)
> > > 	{
> > > 		WRITE_ONCE(*y, 2);
> > 
> > If we change this WRITE_ONCE to a relaxed atomic operation(e.g.
> > xchg_relaxed(y, 2)), both herd and ppcmem said the exist-clause "y = 2
> > /\ 2:r1 = 2 /\ 2:r2 = 0" wouldn't be triggered on PPC.
> > 
> > I guess we will get the same behavior on ARM/ARM64, Will?
> > 
> > If a normal store could break chain, while a RmW atomic won't, do we
> > want to call it out in the document and build our memory model around
> > this?
> 
> I think this is required to work by C11's definition of release sequences,
> so any architecture that claims to support those with the same instructions
> will need this to be forbidden.

Yes.

> Personally, I think that's a bug in C11, because I think it goes too far
> in forbidding some hardware optimisations around relaxed xchg, but it is
> what it is.

The idea at the time (2007 or thereabouts) was that the atomic operation
would have a hard time breaking the causal chain.  To your point, atomic
xchg could presumably update the value and figure out what the previous
value was after the fact.  Maybe we should try to get the committee to
relax the requirement for relaxed xchg, though backwards compatibility
will make that a tough sell.  Might need a new xchg API.

							Thanx, Paul