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Message-Id: <1475894763-64683-2-git-send-email-fenghua.yu@intel.com>
Date: Fri, 7 Oct 2016 19:45:46 -0700
From: "Fenghua Yu" <fenghua.yu@...el.com>
To: "Thomas Gleixner" <tglx@...utronix.de>
Cc: "H. Peter Anvin" <h.peter.anvin@...el.com>,
"Ingo Molnar" <mingo@...e.hu>, "Tony Luck" <tony.luck@...el.com>,
"Peter Zijlstra" <peterz@...radead.org>,
"Stephane Eranian" <eranian@...gle.com>,
"Borislav Petkov" <bp@...e.de>,
"Dave Hansen" <dave.hansen@...el.com>,
"Nilay Vaish" <nilayvaish@...il.com>, "Shaohua Li" <shli@...com>,
"David Carrillo-Cisneros" <davidcc@...gle.com>,
"Ravi V Shankar" <ravi.v.shankar@...el.com>,
"Sai Prakhya" <sai.praneeth.prakhya@...el.com>,
"Vikas Shivappa" <vikas.shivappa@...ux.intel.com>,
"linux-kernel" <linux-kernel@...r.kernel.org>,
"x86" <x86@...nel.org>, "Fenghua Yu" <fenghua.yu@...el.com>
Subject: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id
From: Fenghua Yu <fenghua.yu@...el.com>
Add an ABI document entry for /sys/devices/system/cpu/cpu*/cache/index*/id.
Signed-off-by: Fenghua Yu <fenghua.yu@...el.com>
Signed-off-by: Tony Luck <tony.luck@...el.com>
---
Documentation/ABI/testing/sysfs-devices-system-cpu | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index 4987417..b1c3d69 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -272,6 +272,22 @@ Description: Parameters for the CPU cache attributes
the modified cache line is written to main
memory only when it is replaced
+
+What: /sys/devices/system/cpu/cpu*/cache/index*/id
+Date: September 2016
+Contact: Linux kernel mailing list <linux-kernel@...r.kernel.org>
+Description: Cache id
+
+ The id provides a unique name for a specific instance of
+ a cache of a particular type. E.g. there may be a level
+ 3 unified cache on each socket in a server and we may
+ assign them ids 0, 1, 2, ...
+
+ Note that id value may not be contiguous. E.g. level 1
+ caches typically exist per core, but there may not be a
+ power of two cores on a socket, so these caches may be
+ numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ...
+
What: /sys/devices/system/cpu/cpuX/cpufreq/throttle_stats
/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/turbo_stat
/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/sub_turbo_stat
--
2.5.0
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