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Message-ID: <CACbG308vJ45kM6G22Rketr+BZRrrCa_1R3gg4XNxiMRWtLC1gg@mail.gmail.com>
Date: Tue, 11 Oct 2016 11:48:56 -0500
From: Nilay Vaish <nilayvaish@...il.com>
To: "Luck, Tony" <tony.luck@...el.com>
Cc: Fenghua Yu <fenghua.yu@...el.com>,
Thomas Gleixner <tglx@...utronix.de>,
"H. Peter Anvin" <h.peter.anvin@...el.com>,
Ingo Molnar <mingo@...e.hu>,
Peter Zijlstra <peterz@...radead.org>,
Stephane Eranian <eranian@...gle.com>,
Borislav Petkov <bp@...e.de>,
Dave Hansen <dave.hansen@...el.com>, Shaohua Li <shli@...com>,
David Carrillo-Cisneros <davidcc@...gle.com>,
Ravi V Shankar <ravi.v.shankar@...el.com>,
Sai Prakhya <sai.praneeth.prakhya@...el.com>,
Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for
cache id
On 10 October 2016 at 11:45, Luck, Tony <tony.luck@...el.com> wrote:
> On Sat, Oct 08, 2016 at 12:11:08PM -0500, Nilay Vaish wrote:
>> On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@...el.com> wrote:
>> > From: Fenghua Yu <fenghua.yu@...el.com>
>
>> > + caches typically exist per core, but there may not be a
>> > + power of two cores on a socket, so these caches may be
>> > + numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ...
>> > +
>>
>> While it is ok that the caches are not numbered contiguously, it is
>> unclear how this is related to number of cores on a socket being a
>> power of 2 or not.
>
> That's a side effect of the x86 algorithm to generate the unique ID
> which uses a shift to put the socket number in some upper bits while
> leaving the "id within a socket" in the low bits.
>
> I don't think it worth documenting here, but I noticed that we don't
> keep the IDs within a core contguous either. On my 24 core Broadwell
> they are not 0 ... 23 then a gap from 24 to 31. I actually have on
> socket 0:
>
> 0, 1, 2, 3, 4, 5
> 8, 9, 10, 11, 12, 13
> 16, 17, 18, 19, 20, 21
> 24, 25, 26, 27, 28, 29
>
Thanks for the info.
--
Nilay
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