linux-kernel - Re: [PATCH v1 2/4] Add enabling of the R3 MWAIT during boot for KNL

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Message-ID: <20161012103600.GB3535@nazgul.tnic>
Date:   Wed, 12 Oct 2016 12:36:01 +0200
From:   Borislav Petkov <bp@...e.de>
To:     Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
Cc:     tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
        x86@...nel.org, dave.hansen@...ux.intel.com,
        linux-kernel@...r.kernel.org, lukasz.daniluk@...el.com,
        james.h.cownie@...el.com
Subject: Re: [PATCH v1 2/4] Add enabling of the R3 MWAIT during boot for KNL

On Wed, Oct 12, 2016 at 12:13:08PM +0200, Grzegorz Andrejczuk wrote:
> If processor is Intel Xeon Phi we enable user-level mwait feature.
> Enabling this feature suppreses invalid-opcode error, when MONITOR/MWAIT
> is called from ring 3.
> 
> Change-Id: I1c7defb99296b022790a068a6c725b3e860cd68c
> Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
> ---
>  arch/x86/kernel/cpu/intel.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index fcd484d..7f0f01a 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -61,6 +61,14 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
>  	}
>  }
>  
> +static int phir3mwait = 1;
> +static int __init phir3mwait_disable(char *value)
> +{
> +	phir3mwait = 0;
> +	return 1;
> +}
> +__setup("intel-phir3mwait=disable", phir3mwait_disable);

That's a lot of typing on the cmdline. "r3mwait=disable" looks just as
fine to me, for example.

>  static void early_init_intel(struct cpuinfo_x86 *c)
>  {
>  	u64 misc_enable;
> @@ -211,6 +219,24 @@ static void early_init_intel(struct cpuinfo_x86 *c)
>  	}
>  
>  	check_mpx_erratum(c);
> +
> +	/*
> +	* Setting ring 3 MONITOR/MWAIT for all threads
> +	* when CPU is Xeon Phi Family x200
> +	* This can be disabled with phir3mwait=disable cmdline switch.
> +	* We preserve the reserved values and set only 2nd bit.
> +	* Ref:
> +	* https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait
> +	*/
> +	if (c->x86 == 6 &&
> +	    c->x86_model == INTEL_FAM6_XEON_PHI_KNL &&
> +	    phir3mwait) {
> +		u64 prev;
> +
> +		rdmsrl(MSR_PHI_MISC_THD_FEATURE_ENABLE, prev);
> +		wrmsrl(MSR_PHI_MISC_THD_FEATURE_ENABLE,
> +		       prev | MSR_PHI_MISC_THD_FEATURE_ENABLE_R3MWAIT);

Wanna test the MSR_PHI_MISC_THD_FEATURE_ENABLE_R3MWAIT bit before doing
the MSR write?

Btw, you might want to shorten those define names - they're huuge.

-- 
Regards/Gruss,
    Boris.

SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
--