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Message-ID: <CANRm+CxuJzYfoH2DHt_gESn+gtdiHfauZEtNUODZMuAsgAiJew@mail.gmail.com>
Date:   Thu, 13 Oct 2016 19:52:09 +0800
From:   Wanpeng Li <kernellwp@...il.com>
To:     Radim Krčmář <rkrcmar@...hat.com>
Cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        kvm <kvm@...r.kernel.org>, Paolo Bonzini <pbonzini@...hat.com>,
        Yunhong Jiang <yunhong.jiang@...el.com>,
        Wanpeng Li <wanpeng.li@...mail.com>
Subject: Re: [PATCH RFC V2 2/2] KVM: x86: Support using the VMX preemption
 timer for APIC Timer periodic/oneshot mode

2016-10-13 19:38 GMT+08:00 Wanpeng Li <kernellwp@...il.com>:
> 2016-10-13 1:41 GMT+08:00 Radim Krčmář <rkrcmar@...hat.com>:
>> 2016-10-12 14:52+0800, Wanpeng Li:

[...]

>>> @@ -1711,8 +1753,7 @@ u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
>>>  {
>>>       struct kvm_lapic *apic = vcpu->arch.apic;
>>>
>>> -     if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
>>> -                     apic_lvtt_period(apic))
>>
>> rdmsr MSR_IA32_TSCDEADLINE has to return 0 when the timer is not in tsc
>> deadline mode, so the condition should stay.  (and check for
>> apic_lvtt_tscdeadline(), but that is a unrelated cleanup.)

Actually I modify this function to get apic->lapic_timer.tscdeadline
in kvm_arch_vcpu_load() for periodic/oneshot mode, I introduce another
function to handle this in order to avoid break rdmsr
MSR_IA32_TSCDEADLINE sanity check in RFC V3.

Regards,
Wanpeng Li

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