linux-kernel - Re: [PATCH v3 1/4] Add R3MWAIT register and bit to msr-info.h

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Message-ID: <alpine.DEB.2.20.1610131724200.7777@nanos>
Date:   Thu, 13 Oct 2016 17:28:37 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
cc:     mingo@...hat.com, hpa@...or.com, x86@...nel.org, bp@...e.de,
        dave.hansen@...ux.intel.com, linux-kernel@...r.kernel.org,
        lukasz.daniluk@...el.com, james.h.cownie@...el.com,
        jacob.jun.pan@...el.com
Subject: Re: [PATCH v3 1/4] Add R3MWAIT register and bit to msr-info.h

On Thu, 13 Oct 2016, Grzegorz Andrejczuk wrote:

> Subject: [PATCH v3 1/4] Add R3MWAIT register and bit to msr-info.h

Did you ever notice that all patches have a subsystem related prefix before
the sentence decribing the change? 

See Documentation/SubmittingPatches. Also git log some/file might give you an idea.

> This commit adds this register prefixed by PHI and bit to msr-info.h
> Reference:
> https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait
> Blog entry is a temporary solution, MSR will be present in the next SDM.

Why do you think that the blog entry link in the changelog does not have
the same issues as the link the code comment?

Just copy the relevant bits into the changelog and be done with it.

Thanks,

	tglx