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Date: Thu, 13 Oct 2016 13:21:31 -0300
From: Arnaldo Carvalho de Melo <acme@...nel.org>
To: Ingo Molnar <mingo@...nel.org>
Cc: linux-kernel@...r.kernel.org, Linux Weekly News <lwn@....net>,
Andi Kleen <ak@...ux.intel.com>, Jiri Olsa <jolsa@...hat.com>,
Sukadev Bhattiprolu <sukadev@...ux.vnet.ibm.com>,
Arnaldo Carvalho de Melo <acme@...hat.com>
Subject: [PATCH 18/27] perf jevents: Add NehalemEX V2 event file
From: Andi Kleen <ak@...ux.intel.com>
Add a Intel event file for perf.
Signed-off-by: Andi Kleen <ak@...ux.intel.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: Sukadev Bhattiprolu <sukadev@...ux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-ls90fv1f9japmtqbwfr28acf@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@...hat.com>
---
.../perf/pmu-events/arch/x86/NehalemEX/Cache.json | 3184 ++++++++++++++++++++
.../arch/x86/NehalemEX/Floating-point.json | 229 ++
.../pmu-events/arch/x86/NehalemEX/Frontend.json | 26 +
.../perf/pmu-events/arch/x86/NehalemEX/Memory.json | 739 +++++
.../perf/pmu-events/arch/x86/NehalemEX/Other.json | 210 ++
.../pmu-events/arch/x86/NehalemEX/Pipeline.json | 881 ++++++
.../arch/x86/NehalemEX/Virtual-Memory.json | 109 +
tools/perf/pmu-events/arch/x86/mapfile.csv | 1 +
8 files changed, 5379 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/x86/NehalemEX/Cache.json
create mode 100644 tools/perf/pmu-events/arch/x86/NehalemEX/Floating-point.json
create mode 100644 tools/perf/pmu-events/arch/x86/NehalemEX/Frontend.json
create mode 100644 tools/perf/pmu-events/arch/x86/NehalemEX/Memory.json
create mode 100644 tools/perf/pmu-events/arch/x86/NehalemEX/Other.json
create mode 100644 tools/perf/pmu-events/arch/x86/NehalemEX/Pipeline.json
create mode 100644 tools/perf/pmu-events/arch/x86/NehalemEX/Virtual-Memory.json
diff --git a/tools/perf/pmu-events/arch/x86/NehalemEX/Cache.json b/tools/perf/pmu-events/arch/x86/NehalemEX/Cache.json
new file mode 100644
index 000000000000..21a0f8fd057e
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/NehalemEX/Cache.json
@@ -0,0 +1,3184 @@
+[
+ {
+ "EventCode": "0x63",
+ "Counter": "0,1",
+ "UMask": "0x2",
+ "EventName": "CACHE_LOCK_CYCLES.L1D",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles L1D locked"
+ },
+ {
+ "EventCode": "0x63",
+ "Counter": "0,1",
+ "UMask": "0x1",
+ "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles L1D and L2 locked"
+ },
+ {
+ "EventCode": "0x51",
+ "Counter": "0,1",
+ "UMask": "0x4",
+ "EventName": "L1D.M_EVICT",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1D cache lines replaced in M state"
+ },
+ {
+ "EventCode": "0x51",
+ "Counter": "0,1",
+ "UMask": "0x2",
+ "EventName": "L1D.M_REPL",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1D cache lines allocated in the M state"
+ },
+ {
+ "EventCode": "0x51",
+ "Counter": "0,1",
+ "UMask": "0x8",
+ "EventName": "L1D.M_SNOOP_EVICT",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1D snoop eviction of cache lines in M state"
+ },
+ {
+ "EventCode": "0x51",
+ "Counter": "0,1",
+ "UMask": "0x1",
+ "EventName": "L1D.REPL",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache lines allocated"
+ },
+ {
+ "EventCode": "0x43",
+ "Counter": "0,1",
+ "UMask": "0x1",
+ "EventName": "L1D_ALL_REF.ANY",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "All references to the L1 data cache"
+ },
+ {
+ "EventCode": "0x43",
+ "Counter": "0,1",
+ "UMask": "0x2",
+ "EventName": "L1D_ALL_REF.CACHEABLE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cacheable reads and writes"
+ },
+ {
+ "EventCode": "0x40",
+ "Counter": "0,1",
+ "UMask": "0x4",
+ "EventName": "L1D_CACHE_LD.E_STATE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache read in E state"
+ },
+ {
+ "EventCode": "0x40",
+ "Counter": "0,1",
+ "UMask": "0x1",
+ "EventName": "L1D_CACHE_LD.I_STATE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache read in I state (misses)"
+ },
+ {
+ "EventCode": "0x40",
+ "Counter": "0,1",
+ "UMask": "0x8",
+ "EventName": "L1D_CACHE_LD.M_STATE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache read in M state"
+ },
+ {
+ "EventCode": "0x40",
+ "Counter": "0,1",
+ "UMask": "0xf",
+ "EventName": "L1D_CACHE_LD.MESI",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache reads"
+ },
+ {
+ "EventCode": "0x40",
+ "Counter": "0,1",
+ "UMask": "0x2",
+ "EventName": "L1D_CACHE_LD.S_STATE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache read in S state"
+ },
+ {
+ "EventCode": "0x42",
+ "Counter": "0,1",
+ "UMask": "0x4",
+ "EventName": "L1D_CACHE_LOCK.E_STATE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache load locks in E state"
+ },
+ {
+ "EventCode": "0x42",
+ "Counter": "0,1",
+ "UMask": "0x1",
+ "EventName": "L1D_CACHE_LOCK.HIT",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache load lock hits"
+ },
+ {
+ "EventCode": "0x42",
+ "Counter": "0,1",
+ "UMask": "0x8",
+ "EventName": "L1D_CACHE_LOCK.M_STATE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache load locks in M state"
+ },
+ {
+ "EventCode": "0x42",
+ "Counter": "0,1",
+ "UMask": "0x2",
+ "EventName": "L1D_CACHE_LOCK.S_STATE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache load locks in S state"
+ },
+ {
+ "EventCode": "0x53",
+ "Counter": "0,1",
+ "UMask": "0x1",
+ "EventName": "L1D_CACHE_LOCK_FB_HIT",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1D load lock accepted in fill buffer"
+ },
+ {
+ "EventCode": "0x52",
+ "Counter": "0,1",
+ "UMask": "0x1",
+ "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1D prefetch load lock accepted in fill buffer"
+ },
+ {
+ "EventCode": "0x41",
+ "Counter": "0,1",
+ "UMask": "0x4",
+ "EventName": "L1D_CACHE_ST.E_STATE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache stores in E state"
+ },
+ {
+ "EventCode": "0x41",
+ "Counter": "0,1",
+ "UMask": "0x8",
+ "EventName": "L1D_CACHE_ST.M_STATE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache stores in M state"
+ },
+ {
+ "EventCode": "0x41",
+ "Counter": "0,1",
+ "UMask": "0x2",
+ "EventName": "L1D_CACHE_ST.S_STATE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1 data cache stores in S state"
+ },
+ {
+ "EventCode": "0x4E",
+ "Counter": "0,1",
+ "UMask": "0x2",
+ "EventName": "L1D_PREFETCH.MISS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L1D hardware prefetch misses"
+ },
+ {
+ "EventCode": "0x4E",
+ "Counter": "0,1",
+ "UMask": "0x1",
+ "EventName": "L1D_PREFETCH.REQUESTS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L1D hardware prefetch requests"
+ },
+ {
+ "EventCode": "0x4E",
+ "Counter": "0,1",
+ "UMask": "0x4",
+ "EventName": "L1D_PREFETCH.TRIGGERS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L1D hardware prefetch requests triggered"
+ },
+ {
+ "EventCode": "0x28",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "L1D_WB_L2.E_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L1 writebacks to L2 in E state"
+ },
+ {
+ "EventCode": "0x28",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "L1D_WB_L2.I_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L1 writebacks to L2 in I state (misses)"
+ },
+ {
+ "EventCode": "0x28",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "L1D_WB_L2.M_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L1 writebacks to L2 in M state"
+ },
+ {
+ "EventCode": "0x28",
+ "Counter": "0,1,2,3",
+ "UMask": "0xf",
+ "EventName": "L1D_WB_L2.MESI",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All L1 writebacks to L2"
+ },
+ {
+ "EventCode": "0x28",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "L1D_WB_L2.S_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L1 writebacks to L2 in S state"
+ },
+ {
+ "EventCode": "0x26",
+ "Counter": "0,1,2,3",
+ "UMask": "0xff",
+ "EventName": "L2_DATA_RQSTS.ANY",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "All L2 data requests"
+ },
+ {
+ "EventCode": "0x26",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 data demand loads in E state"
+ },
+ {
+ "EventCode": "0x26",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 data demand loads in I state (misses)"
+ },
+ {
+ "EventCode": "0x26",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 data demand loads in M state"
+ },
+ {
+ "EventCode": "0x26",
+ "Counter": "0,1,2,3",
+ "UMask": "0xf",
+ "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 data demand requests"
+ },
+ {
+ "EventCode": "0x26",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 data demand loads in S state"
+ },
+ {
+ "EventCode": "0x26",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 data prefetches in E state"
+ },
+ {
+ "EventCode": "0x26",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 data prefetches in the I state (misses)"
+ },
+ {
+ "EventCode": "0x26",
+ "Counter": "0,1,2,3",
+ "UMask": "0x80",
+ "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 data prefetches in M state"
+ },
+ {
+ "EventCode": "0x26",
+ "Counter": "0,1,2,3",
+ "UMask": "0xf0",
+ "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "All L2 data prefetches"
+ },
+ {
+ "EventCode": "0x26",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 data prefetches in the S state"
+ },
+ {
+ "EventCode": "0xF1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x7",
+ "EventName": "L2_LINES_IN.ANY",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 lines alloacated"
+ },
+ {
+ "EventCode": "0xF1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "L2_LINES_IN.E_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 lines allocated in the E state"
+ },
+ {
+ "EventCode": "0xF1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "L2_LINES_IN.S_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 lines allocated in the S state"
+ },
+ {
+ "EventCode": "0xF2",
+ "Counter": "0,1,2,3",
+ "UMask": "0xf",
+ "EventName": "L2_LINES_OUT.ANY",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 lines evicted"
+ },
+ {
+ "EventCode": "0xF2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 lines evicted by a demand request"
+ },
+ {
+ "EventCode": "0xF2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 modified lines evicted by a demand request"
+ },
+ {
+ "EventCode": "0xF2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 lines evicted by a prefetch request"
+ },
+ {
+ "EventCode": "0xF2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 modified lines evicted by a prefetch request"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "L2_RQSTS.IFETCH_HIT",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 instruction fetch hits"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "L2_RQSTS.IFETCH_MISS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 instruction fetch misses"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0x30",
+ "EventName": "L2_RQSTS.IFETCHES",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 instruction fetches"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "L2_RQSTS.LD_HIT",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 load hits"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "L2_RQSTS.LD_MISS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 load misses"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0x3",
+ "EventName": "L2_RQSTS.LOADS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 requests"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0xaa",
+ "EventName": "L2_RQSTS.MISS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "All L2 misses"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "L2_RQSTS.PREFETCH_HIT",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 prefetch hits"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0x80",
+ "EventName": "L2_RQSTS.PREFETCH_MISS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 prefetch misses"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0xc0",
+ "EventName": "L2_RQSTS.PREFETCHES",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "All L2 prefetches"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0xff",
+ "EventName": "L2_RQSTS.REFERENCES",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "All L2 requests"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "L2_RQSTS.RFO_HIT",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 RFO hits"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "L2_RQSTS.RFO_MISS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 RFO misses"
+ },
+ {
+ "EventCode": "0x24",
+ "Counter": "0,1,2,3",
+ "UMask": "0xc",
+ "EventName": "L2_RQSTS.RFOS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 RFO requests"
+ },
+ {
+ "EventCode": "0xF0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x80",
+ "EventName": "L2_TRANSACTIONS.ANY",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "All L2 transactions"
+ },
+ {
+ "EventCode": "0xF0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "L2_TRANSACTIONS.FILL",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 fill transactions"
+ },
+ {
+ "EventCode": "0xF0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "L2_TRANSACTIONS.IFETCH",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 instruction fetch transactions"
+ },
+ {
+ "EventCode": "0xF0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "L2_TRANSACTIONS.L1D_WB",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L1D writeback to L2 transactions"
+ },
+ {
+ "EventCode": "0xF0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "L2_TRANSACTIONS.LOAD",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 Load transactions"
+ },
+ {
+ "EventCode": "0xF0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "L2_TRANSACTIONS.PREFETCH",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 prefetch transactions"
+ },
+ {
+ "EventCode": "0xF0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "L2_TRANSACTIONS.RFO",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 RFO transactions"
+ },
+ {
+ "EventCode": "0xF0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "L2_TRANSACTIONS.WB",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "L2 writeback to LLC transactions"
+ },
+ {
+ "EventCode": "0x27",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "L2_WRITE.LOCK.E_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 demand lock RFOs in E state"
+ },
+ {
+ "EventCode": "0x27",
+ "Counter": "0,1,2,3",
+ "UMask": "0xe0",
+ "EventName": "L2_WRITE.LOCK.HIT",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All demand L2 lock RFOs that hit the cache"
+ },
+ {
+ "EventCode": "0x27",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "L2_WRITE.LOCK.I_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 demand lock RFOs in I state (misses)"
+ },
+ {
+ "EventCode": "0x27",
+ "Counter": "0,1,2,3",
+ "UMask": "0x80",
+ "EventName": "L2_WRITE.LOCK.M_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 demand lock RFOs in M state"
+ },
+ {
+ "EventCode": "0x27",
+ "Counter": "0,1,2,3",
+ "UMask": "0xf0",
+ "EventName": "L2_WRITE.LOCK.MESI",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All demand L2 lock RFOs"
+ },
+ {
+ "EventCode": "0x27",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "L2_WRITE.LOCK.S_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 demand lock RFOs in S state"
+ },
+ {
+ "EventCode": "0x27",
+ "Counter": "0,1,2,3",
+ "UMask": "0xe",
+ "EventName": "L2_WRITE.RFO.HIT",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All L2 demand store RFOs that hit the cache"
+ },
+ {
+ "EventCode": "0x27",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "L2_WRITE.RFO.I_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 demand store RFOs in I state (misses)"
+ },
+ {
+ "EventCode": "0x27",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "L2_WRITE.RFO.M_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 demand store RFOs in M state"
+ },
+ {
+ "EventCode": "0x27",
+ "Counter": "0,1,2,3",
+ "UMask": "0xf",
+ "EventName": "L2_WRITE.RFO.MESI",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All L2 demand store RFOs"
+ },
+ {
+ "EventCode": "0x27",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "L2_WRITE.RFO.S_STATE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "L2 demand store RFOs in S state"
+ },
+ {
+ "EventCode": "0x2E",
+ "Counter": "0,1,2,3",
+ "UMask": "0x41",
+ "EventName": "LONGEST_LAT_CACHE.MISS",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Longest latency cache miss"
+ },
+ {
+ "EventCode": "0x2E",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4f",
+ "EventName": "LONGEST_LAT_CACHE.REFERENCE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Longest latency cache reference"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "MEM_INST_RETIRED.LOADS",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Instructions retired which contains a load (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "MEM_INST_RETIRED.STORES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Instructions retired which contains a store (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xCB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xCB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xCB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "MEM_LOAD_RETIRED.L2_HIT",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xCB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
+ "SampleAfterValue": "10000",
+ "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xCB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
+ "SampleAfterValue": "40000",
+ "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xCB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
+ "SampleAfterValue": "40000",
+ "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)"
+ },
+ {
+ "EventCode": "0xB0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore L1 data cache writebacks"
+ },
+ {
+ "EventCode": "0xB2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_REQUESTS_SQ_FULL",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests blocked due to Super Queue full"
+ },
+ {
+ "EventCode": "0xF4",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "SQ_MISC.SPLIT_LOCK",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Super Queue lock splits across a cache line"
+ },
+ {
+ "EventCode": "0x6",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "STORE_BLOCKS.AT_RET",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Loads delayed with at-Retirement block code"
+ },
+ {
+ "EventCode": "0x6",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "STORE_BLOCKS.L1D_BLOCK",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Cacheable loads delayed with L1D block code"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x0",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x400",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "100",
+ "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x80",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "1000",
+ "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x10",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "10000",
+ "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x4000",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "5",
+ "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x800",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "50",
+ "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x100",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "500",
+ "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x20",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "5000",
+ "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x8000",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "3",
+ "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x4",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "50000",
+ "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x1000",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "20",
+ "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x200",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "200",
+ "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x40",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "2000",
+ "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x8",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xB",
+ "MSRValue": "0x2000",
+ "Counter": "3",
+ "UMask": "0x10",
+ "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
+ "MSRIndex": "0x3F6",
+ "SampleAfterValue": "10",
+ "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F11",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF11",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore data reads",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8011",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x111",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x211",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x411",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x711",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4711",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1811",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3811",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1011",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x811",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F44",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF44",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore code reads",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8044",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x144",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x244",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x444",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x744",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4744",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1844",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3844",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1044",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x844",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7FFF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFFFF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore requests",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x80FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x47FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x18FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x38FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x10FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F22",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF22",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore RFO requests",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8022",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x122",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x222",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x422",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x722",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4722",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1822",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3822",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1022",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x822",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F08",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks to any cache or DRAM.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF08",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore writebacks",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8008",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x108",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x408",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x708",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks to the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4708",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1808",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks to a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3808",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1008",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x808",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F77",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF77",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore code or data read requests",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8077",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x177",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x277",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x477",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x777",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4777",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1877",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3877",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1077",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x877",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F33",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore request = all data, response = any cache_dram",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF33",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore request = all data, response = any location",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8033",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x133",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x233",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x433",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x733",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore request = all data, response = local cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4733",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore request = all data, response = local cache or dram",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1833",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore request = all data, response = remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3833",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore request = all data, response = remote cache or dram",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1033",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x833",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F03",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF03",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore demand data requests",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8003",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x103",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x203",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x403",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x703",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4703",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1803",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3803",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1003",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x803",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F01",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF01",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore demand data reads",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8001",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x101",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x201",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x401",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x701",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4701",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1801",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3801",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1001",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x801",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F04",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF04",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore demand code reads",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8004",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x104",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x204",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x404",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x704",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4704",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1804",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3804",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1004",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x804",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F02",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF02",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore demand RFO requests",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8002",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x102",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x202",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x402",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x702",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4702",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1802",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3802",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1002",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x802",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F80",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF80",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore other requests",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8080",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x180",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x280",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x480",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x780",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4780",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1880",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3880",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1080",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x880",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F30",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF30",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore prefetch data requests",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8030",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x130",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x230",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x430",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x730",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4730",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1830",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3830",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1030",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x830",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F10",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF10",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore prefetch data reads",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8010",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x110",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x210",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x410",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x710",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4710",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1810",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3810",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1010",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x810",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F40",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF40",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore prefetch code reads",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8040",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x140",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x240",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x440",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x740",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4740",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1840",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3840",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1040",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x840",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F20",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF20",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore prefetch RFO requests",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8020",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x120",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x220",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x420",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x720",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4720",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1820",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3820",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1020",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x820",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x7F70",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xFF70",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "All offcore prefetch requests",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x8070",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x170",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x270",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x470",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x770",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4770",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1870",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x3870",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x1070",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x870",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
+ "Offcore": "1"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/NehalemEX/Floating-point.json b/tools/perf/pmu-events/arch/x86/NehalemEX/Floating-point.json
new file mode 100644
index 000000000000..7d2f71a9dee3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/NehalemEX/Floating-point.json
@@ -0,0 +1,229 @@
+[
+ {
+ "PEBS": "1",
+ "EventCode": "0xF7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "FP_ASSIST.ALL",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "X87 Floating point assists (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xF7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "FP_ASSIST.INPUT",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xF7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "FP_ASSIST.OUTPUT",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)"
+ },
+ {
+ "EventCode": "0x10",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "FP_COMP_OPS_EXE.MMX",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "MMX Uops"
+ },
+ {
+ "EventCode": "0x10",
+ "Counter": "0,1,2,3",
+ "UMask": "0x80",
+ "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "SSE* FP double precision Uops"
+ },
+ {
+ "EventCode": "0x10",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "FP_COMP_OPS_EXE.SSE_FP",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "SSE and SSE2 FP Uops"
+ },
+ {
+ "EventCode": "0x10",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "SSE FP packed Uops"
+ },
+ {
+ "EventCode": "0x10",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "SSE FP scalar Uops"
+ },
+ {
+ "EventCode": "0x10",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "SSE* FP single precision Uops"
+ },
+ {
+ "EventCode": "0x10",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "SSE2 integer Uops"
+ },
+ {
+ "EventCode": "0x10",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "FP_COMP_OPS_EXE.X87",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Computational floating-point operations executed"
+ },
+ {
+ "EventCode": "0xCC",
+ "Counter": "0,1,2,3",
+ "UMask": "0x3",
+ "EventName": "FP_MMX_TRANS.ANY",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "All Floating Point to and from MMX transitions"
+ },
+ {
+ "EventCode": "0xCC",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "FP_MMX_TRANS.TO_FP",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Transitions from MMX to Floating Point instructions"
+ },
+ {
+ "EventCode": "0xCC",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "FP_MMX_TRANS.TO_MMX",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Transitions from Floating Point to MMX instructions"
+ },
+ {
+ "EventCode": "0x12",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "SIMD_INT_128.PACK",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "128 bit SIMD integer pack operations"
+ },
+ {
+ "EventCode": "0x12",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "SIMD_INT_128.PACKED_ARITH",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "128 bit SIMD integer arithmetic operations"
+ },
+ {
+ "EventCode": "0x12",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "SIMD_INT_128.PACKED_LOGICAL",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "128 bit SIMD integer logical operations"
+ },
+ {
+ "EventCode": "0x12",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "SIMD_INT_128.PACKED_MPY",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "128 bit SIMD integer multiply operations"
+ },
+ {
+ "EventCode": "0x12",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "SIMD_INT_128.PACKED_SHIFT",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "128 bit SIMD integer shift operations"
+ },
+ {
+ "EventCode": "0x12",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "SIMD_INT_128.SHUFFLE_MOVE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "128 bit SIMD integer shuffle/move operations"
+ },
+ {
+ "EventCode": "0x12",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "SIMD_INT_128.UNPACK",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "128 bit SIMD integer unpack operations"
+ },
+ {
+ "EventCode": "0xFD",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "SIMD_INT_64.PACK",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD integer 64 bit pack operations"
+ },
+ {
+ "EventCode": "0xFD",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "SIMD_INT_64.PACKED_ARITH",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD integer 64 bit arithmetic operations"
+ },
+ {
+ "EventCode": "0xFD",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "SIMD_INT_64.PACKED_LOGICAL",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD integer 64 bit logical operations"
+ },
+ {
+ "EventCode": "0xFD",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "SIMD_INT_64.PACKED_MPY",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD integer 64 bit packed multiply operations"
+ },
+ {
+ "EventCode": "0xFD",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "SIMD_INT_64.PACKED_SHIFT",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD integer 64 bit shift operations"
+ },
+ {
+ "EventCode": "0xFD",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "SIMD_INT_64.SHUFFLE_MOVE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD integer 64 bit shuffle/move operations"
+ },
+ {
+ "EventCode": "0xFD",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "SIMD_INT_64.UNPACK",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD integer 64 bit unpack operations"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/NehalemEX/Frontend.json b/tools/perf/pmu-events/arch/x86/NehalemEX/Frontend.json
new file mode 100644
index 000000000000..e5e21e03444d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/NehalemEX/Frontend.json
@@ -0,0 +1,26 @@
+[
+ {
+ "EventCode": "0xD0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "MACRO_INSTS.DECODED",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Instructions decoded"
+ },
+ {
+ "EventCode": "0xA6",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "MACRO_INSTS.FUSIONS_DECODED",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Macro-fused instructions decoded"
+ },
+ {
+ "EventCode": "0x19",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "TWO_UOP_INSTS_DECODED",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Two Uop instructions decoded"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/NehalemEX/Memory.json b/tools/perf/pmu-events/arch/x86/NehalemEX/Memory.json
new file mode 100644
index 000000000000..f914a4525b65
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/NehalemEX/Memory.json
@@ -0,0 +1,739 @@
+[
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6011",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF811",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4011",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2011",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6044",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF844",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4044",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2044",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x60FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF8FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x40FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x20FF",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore requests satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6022",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF822",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4022",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2022",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6008",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks to any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF808",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4008",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks to the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2008",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore writebacks to a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6077",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF877",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4077",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2077",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6033",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore request = all data, response = any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF833",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore request = all data, response = any LLC miss",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4033",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2033",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6003",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF803",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4003",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2003",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6001",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF801",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4001",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2001",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6004",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF804",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4004",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2004",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6002",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF802",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4002",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2002",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6080",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF880",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2080",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore other requests satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6030",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF830",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4030",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2030",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6010",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF810",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4010",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2010",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6040",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF840",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4040",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2040",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6020",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF820",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4020",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2020",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x6070",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0xF870",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests that missed the LLC",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x4070",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
+ "Offcore": "1"
+ },
+ {
+ "EventCode": "0xB7",
+ "MSRValue": "0x2070",
+ "Counter": "2",
+ "UMask": "0x1",
+ "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
+ "MSRIndex": "0x1A6",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
+ "Offcore": "1"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/NehalemEX/Other.json b/tools/perf/pmu-events/arch/x86/NehalemEX/Other.json
new file mode 100644
index 000000000000..af0860622445
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/NehalemEX/Other.json
@@ -0,0 +1,210 @@
+[
+ {
+ "EventCode": "0xE8",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "BPU_CLEARS.EARLY",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Early Branch Prediciton Unit clears"
+ },
+ {
+ "EventCode": "0xE8",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "BPU_CLEARS.LATE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Late Branch Prediction Unit clears"
+ },
+ {
+ "EventCode": "0xE5",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "BPU_MISSED_CALL_RET",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Branch prediction unit missed call or return"
+ },
+ {
+ "EventCode": "0xD5",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "ES_REG_RENAMES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "ES segment renames"
+ },
+ {
+ "EventCode": "0x6C",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "IO_TRANSACTIONS",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "I/O transactions"
+ },
+ {
+ "EventCode": "0x80",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "L1I.CYCLES_STALLED",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1I instruction fetch stall cycles"
+ },
+ {
+ "EventCode": "0x80",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "L1I.HITS",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1I instruction fetch hits"
+ },
+ {
+ "EventCode": "0x80",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "L1I.MISSES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1I instruction fetch misses"
+ },
+ {
+ "EventCode": "0x80",
+ "Counter": "0,1,2,3",
+ "UMask": "0x3",
+ "EventName": "L1I.READS",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "L1I Instruction fetches"
+ },
+ {
+ "EventCode": "0x82",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "LARGE_ITLB.HIT",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Large ITLB hit"
+ },
+ {
+ "EventCode": "0x13",
+ "Counter": "0,1,2,3",
+ "UMask": "0x7",
+ "EventName": "LOAD_DISPATCH.ANY",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "All loads dispatched"
+ },
+ {
+ "EventCode": "0x13",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "LOAD_DISPATCH.MOB",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Loads dispatched from the MOB"
+ },
+ {
+ "EventCode": "0x13",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "LOAD_DISPATCH.RS",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Loads dispatched that bypass the MOB"
+ },
+ {
+ "EventCode": "0x13",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "LOAD_DISPATCH.RS_DELAYED",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Loads dispatched from stage 305"
+ },
+ {
+ "EventCode": "0x7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "PARTIAL_ADDRESS_ALIAS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "False dependencies due to partial address aliasing"
+ },
+ {
+ "EventCode": "0xD2",
+ "Counter": "0,1,2,3",
+ "UMask": "0xf",
+ "EventName": "RAT_STALLS.ANY",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "All RAT stall cycles"
+ },
+ {
+ "EventCode": "0xD2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "RAT_STALLS.FLAGS",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Flag stall cycles"
+ },
+ {
+ "EventCode": "0xD2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "RAT_STALLS.REGISTERS",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Partial register stall cycles"
+ },
+ {
+ "EventCode": "0xD2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "RAT_STALLS.ROB_READ_PORT",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "ROB read port stalls cycles"
+ },
+ {
+ "EventCode": "0xD2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "RAT_STALLS.SCOREBOARD",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Scoreboard stall cycles"
+ },
+ {
+ "EventCode": "0x4",
+ "Counter": "0,1,2,3",
+ "UMask": "0x7",
+ "EventName": "SB_DRAIN.ANY",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "All Store buffer stall cycles"
+ },
+ {
+ "EventCode": "0xD4",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "SEG_RENAME_STALLS",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Segment rename stall cycles"
+ },
+ {
+ "EventCode": "0xB8",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "SNOOP_RESPONSE.HIT",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Thread responded HIT to snoop"
+ },
+ {
+ "EventCode": "0xB8",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "SNOOP_RESPONSE.HITE",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Thread responded HITE to snoop"
+ },
+ {
+ "EventCode": "0xB8",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "SNOOP_RESPONSE.HITM",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Thread responded HITM to snoop"
+ },
+ {
+ "EventCode": "0xF6",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "SQ_FULL_STALL_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Super Queue full stall cycles"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/NehalemEX/Pipeline.json b/tools/perf/pmu-events/arch/x86/NehalemEX/Pipeline.json
new file mode 100644
index 000000000000..41006ddcd893
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/NehalemEX/Pipeline.json
@@ -0,0 +1,881 @@
+[
+ {
+ "EventCode": "0x14",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "ARITH.CYCLES_DIV_BUSY",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles the divider is busy"
+ },
+ {
+ "EventCode": "0x14",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "ARITH.DIV",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Divide Operations executed",
+ "CounterMask": "1",
+ "EdgeDetect": "1"
+ },
+ {
+ "EventCode": "0x14",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "ARITH.MUL",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Multiply operations executed"
+ },
+ {
+ "EventCode": "0xE6",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "BACLEAR.BAD_TARGET",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "BACLEAR asserted with bad target address"
+ },
+ {
+ "EventCode": "0xE6",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "BACLEAR.CLEAR",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "BACLEAR asserted, regardless of cause "
+ },
+ {
+ "EventCode": "0xA7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "BACLEAR_FORCE_IQ",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Instruction queue forced BACLEAR"
+ },
+ {
+ "EventCode": "0xE0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "BR_INST_DECODED",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Branch instructions decoded"
+ },
+ {
+ "EventCode": "0x88",
+ "Counter": "0,1,2,3",
+ "UMask": "0x7f",
+ "EventName": "BR_INST_EXEC.ANY",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Branch instructions executed"
+ },
+ {
+ "EventCode": "0x88",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "BR_INST_EXEC.COND",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Conditional branch instructions executed"
+ },
+ {
+ "EventCode": "0x88",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "BR_INST_EXEC.DIRECT",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Unconditional branches executed"
+ },
+ {
+ "EventCode": "0x88",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Unconditional call branches executed"
+ },
+ {
+ "EventCode": "0x88",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Indirect call branches executed"
+ },
+ {
+ "EventCode": "0x88",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Indirect non call branches executed"
+ },
+ {
+ "EventCode": "0x88",
+ "Counter": "0,1,2,3",
+ "UMask": "0x30",
+ "EventName": "BR_INST_EXEC.NEAR_CALLS",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Call branches executed"
+ },
+ {
+ "EventCode": "0x88",
+ "Counter": "0,1,2,3",
+ "UMask": "0x7",
+ "EventName": "BR_INST_EXEC.NON_CALLS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "All non call branches executed"
+ },
+ {
+ "EventCode": "0x88",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "BR_INST_EXEC.RETURN_NEAR",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Indirect return branches executed"
+ },
+ {
+ "EventCode": "0x88",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "BR_INST_EXEC.TAKEN",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Taken branches executed"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Retired branch instructions (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "BR_INST_RETIRED.CONDITIONAL",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Retired conditional branch instructions (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC4",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "BR_INST_RETIRED.NEAR_CALL",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Retired near call instructions (Precise Event)"
+ },
+ {
+ "EventCode": "0x89",
+ "Counter": "0,1,2,3",
+ "UMask": "0x7f",
+ "EventName": "BR_MISP_EXEC.ANY",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Mispredicted branches executed"
+ },
+ {
+ "EventCode": "0x89",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "BR_MISP_EXEC.COND",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Mispredicted conditional branches executed"
+ },
+ {
+ "EventCode": "0x89",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "BR_MISP_EXEC.DIRECT",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Mispredicted unconditional branches executed"
+ },
+ {
+ "EventCode": "0x89",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
+ "SampleAfterValue": "2000",
+ "BriefDescription": "Mispredicted non call branches executed"
+ },
+ {
+ "EventCode": "0x89",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
+ "SampleAfterValue": "2000",
+ "BriefDescription": "Mispredicted indirect call branches executed"
+ },
+ {
+ "EventCode": "0x89",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
+ "SampleAfterValue": "2000",
+ "BriefDescription": "Mispredicted indirect non call branches executed"
+ },
+ {
+ "EventCode": "0x89",
+ "Counter": "0,1,2,3",
+ "UMask": "0x30",
+ "EventName": "BR_MISP_EXEC.NEAR_CALLS",
+ "SampleAfterValue": "2000",
+ "BriefDescription": "Mispredicted call branches executed"
+ },
+ {
+ "EventCode": "0x89",
+ "Counter": "0,1,2,3",
+ "UMask": "0x7",
+ "EventName": "BR_MISP_EXEC.NON_CALLS",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Mispredicted non call branches executed"
+ },
+ {
+ "EventCode": "0x89",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "BR_MISP_EXEC.RETURN_NEAR",
+ "SampleAfterValue": "2000",
+ "BriefDescription": "Mispredicted return branches executed"
+ },
+ {
+ "EventCode": "0x89",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "BR_MISP_EXEC.TAKEN",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Mispredicted taken branches executed"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC5",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "BR_MISP_RETIRED.NEAR_CALL",
+ "SampleAfterValue": "2000",
+ "BriefDescription": "Mispredicted near retired calls (Precise Event)"
+ },
+ {
+ "EventCode": "0x0",
+ "Counter": "Fixed counter 3",
+ "UMask": "0x0",
+ "EventName": "CPU_CLK_UNHALTED.REF",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Reference cycles when thread is not halted (fixed counter)"
+ },
+ {
+ "EventCode": "0x3C",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "CPU_CLK_UNHALTED.REF_P",
+ "SampleAfterValue": "100000",
+ "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)"
+ },
+ {
+ "EventCode": "0x0",
+ "Counter": "Fixed counter 2",
+ "UMask": "0x0",
+ "EventName": "CPU_CLK_UNHALTED.THREAD",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles when thread is not halted (fixed counter)"
+ },
+ {
+ "EventCode": "0x3C",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "EventName": "CPU_CLK_UNHALTED.THREAD_P",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles when thread is not halted (programmable counter)"
+ },
+ {
+ "EventCode": "0x3C",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x0",
+ "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Total CPU cycles",
+ "CounterMask": "2"
+ },
+ {
+ "EventCode": "0x87",
+ "Counter": "0,1,2,3",
+ "UMask": "0xf",
+ "EventName": "ILD_STALL.ANY",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Any Instruction Length Decoder stall cycles"
+ },
+ {
+ "EventCode": "0x87",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "ILD_STALL.IQ_FULL",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Instruction Queue full stall cycles"
+ },
+ {
+ "EventCode": "0x87",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "ILD_STALL.LCP",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Length Change Prefix stall cycles"
+ },
+ {
+ "EventCode": "0x87",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "ILD_STALL.MRU",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Stall cycles due to BPU MRU bypass"
+ },
+ {
+ "EventCode": "0x87",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "ILD_STALL.REGEN",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Regen stall cycles"
+ },
+ {
+ "EventCode": "0x18",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "INST_DECODED.DEC0",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Instructions that must be decoded by decoder 0"
+ },
+ {
+ "EventCode": "0x1E",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "INST_QUEUE_WRITE_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles instructions are written to the instruction queue"
+ },
+ {
+ "EventCode": "0x17",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "INST_QUEUE_WRITES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Instructions written to instruction queue."
+ },
+ {
+ "EventCode": "0x0",
+ "Counter": "Fixed counter 1",
+ "UMask": "0x0",
+ "EventName": "INST_RETIRED.ANY",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Instructions retired (fixed counter)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "INST_RETIRED.ANY_P",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Instructions retired (Programmable counter and Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "INST_RETIRED.MMX",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Retired MMX instructions (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC0",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "INST_RETIRED.TOTAL_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Total cycles (Precise Event)",
+ "CounterMask": "16"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC0",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "INST_RETIRED.X87",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Retired floating-point operations (Precise Event)"
+ },
+ {
+ "EventCode": "0x4C",
+ "Counter": "0,1",
+ "UMask": "0x1",
+ "EventName": "LOAD_HIT_PRE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Load operations conflicting with software prefetches"
+ },
+ {
+ "EventCode": "0xA8",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "LSD.ACTIVE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles when uops were delivered by the LSD",
+ "CounterMask": "1"
+ },
+ {
+ "EventCode": "0xA8",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "LSD.INACTIVE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles no uops were delivered by the LSD",
+ "CounterMask": "1"
+ },
+ {
+ "EventCode": "0x20",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "LSD_OVERFLOW",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Loops that can't stream from the instruction queue"
+ },
+ {
+ "EventCode": "0xC3",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "MACHINE_CLEARS.CYCLES",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Cycles machine clear asserted"
+ },
+ {
+ "EventCode": "0xC3",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "MACHINE_CLEARS.MEM_ORDER",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts"
+ },
+ {
+ "EventCode": "0xC3",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "MACHINE_CLEARS.SMC",
+ "SampleAfterValue": "20000",
+ "BriefDescription": "Self-Modifying Code detected"
+ },
+ {
+ "EventCode": "0xA2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "RESOURCE_STALLS.ANY",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Resource related stall cycles"
+ },
+ {
+ "EventCode": "0xA2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "RESOURCE_STALLS.FPCW",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "FPU control word write stall cycles"
+ },
+ {
+ "EventCode": "0xA2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "RESOURCE_STALLS.LOAD",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Load buffer stall cycles"
+ },
+ {
+ "EventCode": "0xA2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "RESOURCE_STALLS.MXCSR",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "MXCSR rename stall cycles"
+ },
+ {
+ "EventCode": "0xA2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x80",
+ "EventName": "RESOURCE_STALLS.OTHER",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Other Resource related stall cycles"
+ },
+ {
+ "EventCode": "0xA2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "RESOURCE_STALLS.ROB_FULL",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "ROB full stall cycles"
+ },
+ {
+ "EventCode": "0xA2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "RESOURCE_STALLS.RS_FULL",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Reservation Station full stall cycles"
+ },
+ {
+ "EventCode": "0xA2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "RESOURCE_STALLS.STORE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Store buffer stall cycles"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)"
+ },
+ {
+ "EventCode": "0xDB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "UOP_UNFUSION",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uop unfusions due to FP exceptions"
+ },
+ {
+ "EventCode": "0xD1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "UOPS_DECODED.ESP_FOLDING",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Stack pointer instructions decoded"
+ },
+ {
+ "EventCode": "0xD1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "EventName": "UOPS_DECODED.ESP_SYNC",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Stack pointer sync operations"
+ },
+ {
+ "EventCode": "0xD1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops decoded by Microcode Sequencer",
+ "CounterMask": "1"
+ },
+ {
+ "EventCode": "0xD1",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "UOPS_DECODED.STALL_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles no Uops are decoded",
+ "CounterMask": "1"
+ },
+ {
+ "EventCode": "0xB1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x3f",
+ "AnyThread": "1",
+ "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles Uops executed on any port (core count)",
+ "CounterMask": "1"
+ },
+ {
+ "EventCode": "0xB1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1f",
+ "AnyThread": "1",
+ "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
+ "CounterMask": "1"
+ },
+ {
+ "EventCode": "0xB1",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x3f",
+ "AnyThread": "1",
+ "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops executed on any port (core count)",
+ "CounterMask": "1",
+ "EdgeDetect": "1"
+ },
+ {
+ "EventCode": "0xB1",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1f",
+ "AnyThread": "1",
+ "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops executed on ports 0-4 (core count)",
+ "CounterMask": "1",
+ "EdgeDetect": "1"
+ },
+ {
+ "EventCode": "0xB1",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x3f",
+ "AnyThread": "1",
+ "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles no Uops issued on any port (core count)",
+ "CounterMask": "1"
+ },
+ {
+ "EventCode": "0xB1",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1f",
+ "AnyThread": "1",
+ "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
+ "CounterMask": "1"
+ },
+ {
+ "EventCode": "0xB1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "UOPS_EXECUTED.PORT0",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops executed on port 0"
+ },
+ {
+ "EventCode": "0xB1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "UOPS_EXECUTED.PORT015",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops issued on ports 0, 1 or 5"
+ },
+ {
+ "EventCode": "0xB1",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x40",
+ "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
+ "CounterMask": "1"
+ },
+ {
+ "EventCode": "0xB1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "UOPS_EXECUTED.PORT1",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops executed on port 1"
+ },
+ {
+ "EventCode": "0xB1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "AnyThread": "1",
+ "EventName": "UOPS_EXECUTED.PORT2_CORE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops executed on port 2 (core count)"
+ },
+ {
+ "EventCode": "0xB1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x80",
+ "AnyThread": "1",
+ "EventName": "UOPS_EXECUTED.PORT234_CORE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops issued on ports 2, 3 or 4"
+ },
+ {
+ "EventCode": "0xB1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x8",
+ "AnyThread": "1",
+ "EventName": "UOPS_EXECUTED.PORT3_CORE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops executed on port 3 (core count)"
+ },
+ {
+ "EventCode": "0xB1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "AnyThread": "1",
+ "EventName": "UOPS_EXECUTED.PORT4_CORE",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops executed on port 4 (core count)"
+ },
+ {
+ "EventCode": "0xB1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "UOPS_EXECUTED.PORT5",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops executed on port 5"
+ },
+ {
+ "EventCode": "0xE",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "UOPS_ISSUED.ANY",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops issued"
+ },
+ {
+ "EventCode": "0xE",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "AnyThread": "1",
+ "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles no Uops were issued on any thread",
+ "CounterMask": "1"
+ },
+ {
+ "EventCode": "0xE",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "AnyThread": "1",
+ "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles Uops were issued on either thread",
+ "CounterMask": "1"
+ },
+ {
+ "EventCode": "0xE",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "UOPS_ISSUED.FUSED",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Fused Uops issued"
+ },
+ {
+ "EventCode": "0xE",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "UOPS_ISSUED.STALL_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles no Uops were issued",
+ "CounterMask": "1"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles Uops are being retired",
+ "CounterMask": "1"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "UOPS_RETIRED.ANY",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Uops retired (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x4",
+ "EventName": "UOPS_RETIRED.MACRO_FUSED",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Macro-fused Uops retired (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC2",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Retirement slots used (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC2",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "UOPS_RETIRED.STALL_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
+ "CounterMask": "1"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC2",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
+ "CounterMask": "16"
+ },
+ {
+ "PEBS": "2",
+ "EventCode": "0xC0",
+ "Invert": "1",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "Total cycles (Precise Event)",
+ "CounterMask": "16"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/NehalemEX/Virtual-Memory.json b/tools/perf/pmu-events/arch/x86/NehalemEX/Virtual-Memory.json
new file mode 100644
index 000000000000..0596094e0ee9
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/NehalemEX/Virtual-Memory.json
@@ -0,0 +1,109 @@
+[
+ {
+ "EventCode": "0x8",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "DTLB_LOAD_MISSES.ANY",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "DTLB load misses"
+ },
+ {
+ "EventCode": "0x8",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "DTLB load miss caused by low part of address"
+ },
+ {
+ "EventCode": "0x8",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "DTLB second level hit"
+ },
+ {
+ "EventCode": "0x8",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "DTLB load miss page walks complete"
+ },
+ {
+ "EventCode": "0x49",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "DTLB_MISSES.ANY",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "DTLB misses"
+ },
+ {
+ "EventCode": "0x49",
+ "Counter": "0,1,2,3",
+ "UMask": "0x10",
+ "EventName": "DTLB_MISSES.STLB_HIT",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "DTLB first level misses but second level hit"
+ },
+ {
+ "EventCode": "0x49",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "DTLB_MISSES.WALK_COMPLETED",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "DTLB miss page walks"
+ },
+ {
+ "EventCode": "0xAE",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "ITLB_FLUSH",
+ "SampleAfterValue": "2000000",
+ "BriefDescription": "ITLB flushes"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC8",
+ "Counter": "0,1,2,3",
+ "UMask": "0x20",
+ "EventName": "ITLB_MISS_RETIRED",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)"
+ },
+ {
+ "EventCode": "0x85",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "ITLB_MISSES.ANY",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "ITLB miss"
+ },
+ {
+ "EventCode": "0x85",
+ "Counter": "0,1,2,3",
+ "UMask": "0x2",
+ "EventName": "ITLB_MISSES.WALK_COMPLETED",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "ITLB miss page walks"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xCB",
+ "Counter": "0,1,2,3",
+ "UMask": "0x80",
+ "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Retired loads that miss the DTLB (Precise Event)"
+ },
+ {
+ "PEBS": "1",
+ "EventCode": "0xC",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
+ "SampleAfterValue": "200000",
+ "BriefDescription": "Retired stores that miss the DTLB (Precise Event)"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index fa2834961962..634c7fe82670 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -20,3 +20,4 @@ GenuineIntel-6-57,V9,KnightsLanding,core
GenuineIntel-6-1E,V2,NehalemEP,core
GenuineIntel-6-1F,V2,NehalemEP,core
GenuineIntel-6-1A,V2,NehalemEP,core
+GenuineIntel-6-2E,V2,NehalemEX,core
--
2.7.4
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