linux-kernel - [PATCH v4 4/4] x86/phi: Add R3MWAIT to CPU features

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Message-Id: <1476784971-23872-5-git-send-email-grzegorz.andrejczuk@intel.com>
Date:   Tue, 18 Oct 2016 12:02:51 +0200
From:   Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
To:     tglx@...utronix.de, mingo@...hat.com, hpa@...or.com, x86@...nel.org
Cc:     bp@...e.de, dave.hansen@...ux.intel.com,
        linux-kernel@...r.kernel.org, lukasz.daniluk@...el.com,
        james.h.cownie@...el.com, jacob.jun.pan@...el.com,
        Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
Subject: [PATCH v4 4/4] x86/phi: Add R3MWAIT to CPU features

Add cpu feature for ring 3 monitor/mwait.
Set HWCAP2 1st bit during init.

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
---
 arch/x86/include/asm/cpufeatures.h | 2 ++
 arch/x86/kernel/cpu/intel.c        | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 92a8308..d430200 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -71,6 +71,8 @@
 #define X86_FEATURE_RECOVERY	( 2*32+ 0) /* CPU in recovery mode */
 #define X86_FEATURE_LONGRUN	( 2*32+ 1) /* Longrun power control */
 #define X86_FEATURE_LRTI	( 2*32+ 3) /* LongRun table interface */
+/* Xeon Phi x200 ring 3 MONITOR/MWAIT enabled */
+#define X86_FEATURE_PHIR3MWAIT	( 2*32+ 4)
 
 /* Other features, Linux-defined mapping, word 3 */
 /* This range is used for feature bits which conflict or are synthesized */
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1134dca..a2ea905 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -14,6 +14,8 @@
 #include <asm/bugs.h>
 #include <asm/cpu.h>
 #include <asm/intel-family.h>
+#include <asm/hwcap2.h>
+#include <asm/elf.h>
 
 #ifdef CONFIG_X86_64
 #include <linux/topology.h>
@@ -87,6 +89,8 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
 		rdmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
 		msr |= MSR_PHI_MISC_THD_FEATURE_R3MWAIT;
 		wrmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
+		set_cpu_cap(c, X86_FEATURE_PHIR3MWAIT);
+		ELF_HWCAP2 |= HWCAP2_PHIR3MWAIT;
 	}
 }
 
-- 
2.5.1