linux-kernel - Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN

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Message-ID: <20161021054717.GZ3102@twins.programming.kicks-ass.net>
Date:   Fri, 21 Oct 2016 07:47:17 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     Thomas Gleixner <tglx@...utronix.de>
Cc:     Bin Gao <bin.gao@...ux.intel.com>, Ingo Molnar <mingo@...hat.com>,
        "H. Peter Anvin" <hpa@...or.com>,
        John Stultz <john.stultz@...aro.org>, x86@...nel.org,
        linux-kernel@...r.kernel.org, bin.gao@...el.com
Subject: Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag

On Thu, Oct 20, 2016 at 09:37:50PM +0200, Thomas Gleixner wrote:

> Well, we have the same issue on other platforms/models which set the
> reliable flag.

I was not aware we had other platforms doing this, git grep tells me
intel-mid does this as well..

> So one sanity check we can do is to read the IA32_TSC_ADJUST MSR on all
> cores. They should all have the same value (usually 0) or at least have a
> very minimal delta. If that's off by more than 1us then something is fishy
> especially on single socket systems. We could at least WARN about it.
> 
> We could do this in idle occasionally as well, so we can detect the dreaded
> "SMI wants to hide the cycles" crapola.

Indeed, that sounds like the best we can; and probably should; do.