linux-kernel - Re: [PATCH v5] x86/msr: Add write msr notrace to avoid the debug codes splash

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Message-ID: <20161026115003.s2lquaxv5gdwjsie@pd.tnic>
Date:   Wed, 26 Oct 2016 13:50:03 +0200
From:   Borislav Petkov <bp@...en8.de>
To:     Wanpeng Li <kernellwp@...il.com>
Cc:     linux-kernel@...r.kernel.org, Wanpeng Li <wanpeng.li@...mail.com>,
        Ingo Molnar <mingo@...nel.org>, Mike Galbraith <efault@....de>,
        Peter Zijlstra <peterz@...radead.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Paolo Bonzini <pbonzini@...hat.com>
Subject: Re: [PATCH v5] x86/msr: Add write msr notrace to avoid the debug
 codes splash

On Wed, Oct 26, 2016 at 07:35:26PM +0800, Wanpeng Li wrote:
> From: Wanpeng Li <wanpeng.li@...mail.com>
> 
> As Peterz pointed out:
> 
> | The thing is, many many smp_reschedule_interrupt() invocations don't
> | actually execute anything much at all and are only send to tickle the
> | return to user path (which does the actual preemption).
> 
> This patch add write msr notrace to avoid the debug codes splash.
> 
> Suggested-by: Peter Zijlstra <peterz@...radead.org>
> Suggested-by: Paolo Bonzini <pbonzini@...hat.com>
> Cc: Ingo Molnar <mingo@...nel.org>
> Cc: Mike Galbraith <efault@....de>
> Cc: Peter Zijlstra <peterz@...radead.org>
> Cc: Thomas Gleixner <tglx@...utronix.de>
> Cc: Paolo Bonzini <pbonzini@...hat.com>
> Signed-off-by: Wanpeng Li <wanpeng.li@...mail.com>
> ---
>  arch/x86/include/asm/apic.h |  3 ++-
>  arch/x86/include/asm/msr.h  | 15 +++++++++++++++
>  arch/x86/kernel/apic/apic.c |  1 +
>  arch/x86/kernel/kvm.c       |  4 ++--
>  arch/x86/kernel/smp.c       |  2 --
>  5 files changed, 20 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
> index f5aaf6c..a5a0bcf 100644
> --- a/arch/x86/include/asm/apic.h
> +++ b/arch/x86/include/asm/apic.h
> @@ -196,7 +196,7 @@ static inline void native_apic_msr_write(u32 reg, u32 v)
>  
>  static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
>  {
> -	wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
> +	wrmsr_notrace(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
>  }
>  
>  static inline u32 native_apic_msr_read(u32 reg)
> @@ -332,6 +332,7 @@ struct apic {
>  	 * on write for EOI.
>  	 */
>  	void (*eoi_write)(u32 reg, u32 v);
> +	void (*native_eoi_write)(u32 reg, u32 v);
>  	u64 (*icr_read)(void);
>  	void (*icr_write)(u32 low, u32 high);
>  	void (*wait_icr_idle)(void);
> diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
> index b5fee97..afbb221 100644
> --- a/arch/x86/include/asm/msr.h
> +++ b/arch/x86/include/asm/msr.h
> @@ -127,6 +127,21 @@ notrace static inline void native_write_msr(unsigned int msr,
>  }
>  
>  /* Can be uninlined because referenced by paravirt */
> +notrace static inline void native_write_msr_notrace(unsigned int msr,
> +					    unsigned low, unsigned high)
> +{
> +	asm volatile("1: wrmsr\n"
> +		     "2:\n"
> +		     _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_unsafe)
> +		     : : "c" (msr), "a"(low), "d" (high) : "memory");
> +}

Why is this duplicating the inline asm?

This function should be called __native_write_msr_notrace() instead and
then native_write_msr() should do:

notrace static inline void native_write_msr(unsigned int msr,
	                                            unsigned low, unsigned high)
{
	__native_write_msr_notrace(msr, low, high);
	if (msr_tracepoint_active(__tracepoint_write_msr))
		do_trace_write_msr(msr, ((u64)high << 32 | low), 0);
}

This way it is way more clear who calls what.

And this thing should be two patches anyway:

1. change native_write_msr()
2. Add the apic changes.

-- 
Regards/Gruss,
    Boris.

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