linux-kernel - [PATCH 4.8 039/140] powerpc/powernv: Pass CPU-endian PE number to opal_pci_eeh_freeze

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Message-Id: <20161026122222.063781617@linuxfoundation.org>
Date:   Wed, 26 Oct 2016 14:21:39 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Paul Mackerras <paulus@...ba.org>,
        Gavin Shan <gwshan@...ux.vnet.ibm.com>,
        Russell Currey <ruscur@...sell.cc>,
        Michael Ellerman <mpe@...erman.id.au>
Subject: [PATCH 4.8 039/140] powerpc/powernv: Pass CPU-endian PE number to opal_pci_eeh_freeze_clear()

4.8-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Gavin Shan <gwshan@...ux.vnet.ibm.com>

commit d63e51b31e0b655ed0f581b8a8fd4c4b4f8d1919 upstream.

The PE number (@frozen_pe_no), filled by opal_pci_next_error() is in
big-endian format. It should be converted to CPU-endian before it is
passed to opal_pci_eeh_freeze_clear() when clearing the frozen state if
the PE is invalid one. As Michael Ellerman pointed out, the issue is
also detected by sparse:

  eeh-powernv.c:1541:41: warning: incorrect type in argument 2 (different base types)

This passes CPU-endian PE number to opal_pci_eeh_freeze_clear() and it
should be part of commit <0f36db77643b> ("powerpc/eeh: Fix wrong printed
PE number"), which was merged to 4.3 kernel.

Fixes: 71b540adffd9 ("powerpc/powernv: Don't escalate non-existing frozen PE")
Suggested-by: Paul Mackerras <paulus@...ba.org>
Signed-off-by: Gavin Shan <gwshan@...ux.vnet.ibm.com>
Reviewed-by: Russell Currey <ruscur@...sell.cc>
Signed-off-by: Michael Ellerman <mpe@...erman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 arch/powerpc/platforms/powernv/eeh-powernv.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -1538,7 +1538,7 @@ static int pnv_eeh_next_error(struct eeh
 
 				/* Try best to clear it */
 				opal_pci_eeh_freeze_clear(phb->opal_id,
-					frozen_pe_no,
+					be64_to_cpu(frozen_pe_no),
 					OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 				ret = EEH_NEXT_ERR_NONE;
 			} else if ((*pe)->state & EEH_PE_ISOLATED ||