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Message-ID: <alpine.DEB.2.20.1610261627310.4983@nanos>
Date: Wed, 26 Oct 2016 16:28:45 +0200 (CEST)
From: Thomas Gleixner <tglx@...utronix.de>
To: Borislav Petkov <bp@...e.de>
cc: Fenghua Yu <fenghua.yu@...el.com>,
"H. Peter Anvin" <h.peter.anvin@...el.com>,
Ingo Molnar <mingo@...e.hu>, Tony Luck <tony.luck@...el.com>,
Peter Zijlstra <peterz@...radead.org>,
Stephane Eranian <eranian@...gle.com>,
Dave Hansen <dave.hansen@...el.com>,
Nilay Vaish <nilayvaish@...il.com>, Shaohua Li <shli@...com>,
David Carrillo-Cisneros <davidcc@...gle.com>,
Ravi V Shankar <ravi.v.shankar@...el.com>,
Sai Prakhya <sai.praneeth.prakhya@...el.com>,
Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [PATCH v5 04/18] x86/intel_rdt: Feature discovery
On Wed, 26 Oct 2016, Borislav Petkov wrote:
> > +#define X86_FEATURE_CAT_L3 ( 7*32+16) /* Cache Allocation Technology L3 */
> > +#define X86_FEATURE_CAT_L2 ( 7*32+17) /* Cache Allocation Technology L2 */
> > +#define X86_FEATURE_CDP_L3 ( 7*32+18) /* Code and Data Prioritization L3 */
>
> Also, this patch or even better, the whole patchset needs to be at least
> test-merged with tip/master to check for conflicting changes. Like this
> one here:
>
> #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
> #define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
> #define X86_FEATURE_CAT_L3 ( 7*32+16) /* Cache Allocation Technology L3 */
That's an easy one to fixup and I prefer a clean patch against Linus tree
at the moment.
Thanks,
tglx
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