linux-kernel - [PATCH V3 2/6] clk: tegra: add TEGRA30_CLK

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Message-Id: <1477576872-2665-3-git-send-email-mirza.krak@gmail.com>
Date:   Thu, 27 Oct 2016 16:01:08 +0200
From:   Mirza Krak <mirza.krak@...il.com>
To:     swarren@...dotorg.org, thierry.reding@...il.com,
        jonathanh@...dia.com
Cc:     gnurou@...il.com, linux@...linux.org.uk, pdeschrijver@...dia.com,
        pgaikwad@...dia.com, mturquette@...libre.com, sboyd@...eaurora.org,
        robh+dt@...nel.org, mark.rutland@....com,
        devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-clk@...r.kernel.org, Mirza Krak <mirza.krak@...il.com>
Subject: [PATCH V3 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table

From: Mirza Krak <mirza.krak@...il.com>

Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which
is max rate.

The maximum rate value of 127 MHz is pulled from the downstream L4T
kernel.

Signed-off-by: Mirza Krak <mirza.krak@...il.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@...adex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
---

Changes in v2:
- no changes

Changes in v3:
- Added comment in commit message where I got the maximum rates from.

 drivers/clk/tegra/clk-tegra30.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 8e2db5e..67f1677 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1252,6 +1252,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
 	{ TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
 	{ TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
+	{ TEGRA30_CLK_NOR, TEGRA30_CLK_PLL_P, 127000000, 0 },
 	{ TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
--
2.1.4